From patchwork Mon Apr 15 21:14:39 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Figa X-Patchwork-Id: 2446901 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id AFAB7DF2E5 for ; Mon, 15 Apr 2013 21:16:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755578Ab3DOVQA (ORCPT ); Mon, 15 Apr 2013 17:16:00 -0400 Received: from mail-ee0-f51.google.com ([74.125.83.51]:40359 "EHLO mail-ee0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754989Ab3DOVP7 (ORCPT ); Mon, 15 Apr 2013 17:15:59 -0400 Received: by mail-ee0-f51.google.com with SMTP id c4so2418114eek.24 for ; Mon, 15 Apr 2013 14:15:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=Gabk5eOmj8U04/kOTddkfgYpc6Pi8SIZOEaG80zlHbI=; b=mLJMtFBdaYv5PLJsrkBlK+ZUzfB9rlgEORl10TH/uW3rGd2CnCO3snqF/7nM2LA/S0 82ZgkvFzpDt7MnYr3qnRXsbTpQKmkLNhLUp0MrnyzivFzjc3LWvhs/uJ6prb28ovvpOi IQoeY13SRZAoHUnbiTSsDN7+y8ZdJyQy7K3WzzVAcKwlChpz/eV0iFfPsGgfHk0Z4r49 Daf38XrdmgBBZD7TIIsr0I0w8/i2JIipcXNCFlhccTS7RIr4HAeU6/CtR52/gUQ8/Snn YBKe3V3VE0F/ARiHjlFfkIofJx7EFmECY4RZKF5fBPngh/dK+9PJZw0AlX4nUJnj6bXT Hd9w== X-Received: by 10.15.24.71 with SMTP id i47mr55260128eeu.0.1366060558575; Mon, 15 Apr 2013 14:15:58 -0700 (PDT) Received: from flatron.tomeq (87-207-52-162.dynamic.chello.pl. [87.207.52.162]) by mx.google.com with ESMTPS id a2sm27439737eem.11.2013.04.15.14.15.56 (version=TLSv1.2 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 15 Apr 2013 14:15:57 -0700 (PDT) From: Tomasz Figa To: linux-samsung-soc@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, devicetree-discuss@lists.ozlabs.org, kgene.kim@samsung.com, broonie@opensource.wolfsonmicro.com, kwangwoo.lee@gmail.com, jacmet@sunsite.dk, augulis.darius@gmail.com, mcuelenaere@gmail.com, linux@arm.linux.org.uk, Rob Herring , Mark Rutland , Tomasz Figa Subject: [PATCH v5 2/6] ARM: s3c64xx: Skip legacy EINT setup if pinctrl-s3c64xx driver is present Date: Mon, 15 Apr 2013 23:14:39 +0200 Message-Id: <1366060483-20342-3-git-send-email-tomasz.figa@gmail.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1366060483-20342-1-git-send-email-tomasz.figa@gmail.com> References: <1366060483-20342-1-git-send-email-tomasz.figa@gmail.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The new pinctrl-s3c64xx is responsible for EINT handling on DT-enabled platforms. Signed-off-by: Tomasz Figa --- arch/arm/mach-s3c64xx/common.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c index e79ca92..866be9e 100644 --- a/arch/arm/mach-s3c64xx/common.c +++ b/arch/arm/mach-s3c64xx/common.c @@ -365,7 +365,25 @@ static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc) static int __init s3c64xx_init_irq_eint(void) { int irq; - +#if defined(CONFIG_PINCTRL_S3C64XX) + /* + * This gpio driver includes support for device tree support and there + * are platforms using it. In order to maintain compatibility with those + * platforms, and to allow non-dt Exynos4210 platforms to use this + * gpiolib support, a check is added to find out if there is a active + * pin-controller driver support available. If it is available, this + * gpiolib support is ignored and the gpiolib support available in + * pin-controller driver is used. This is a temporary check and will go + * away when all of the Exynos4210 platforms have switched to using + * device tree and the pin-ctrl driver. + */ + struct device_node *pctrl_np; + + pctrl_np = of_find_compatible_node(NULL, NULL, + "samsung,s3c64xx-pinctrl"); + if (pctrl_np && of_device_is_available(pctrl_np)) + return -ENODEV; +#endif for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq); irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));