From patchwork Fri Apr 19 16:38:08 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 2466131 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id AB66DDF25A for ; Fri, 19 Apr 2013 16:38:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030925Ab3DSQia (ORCPT ); Fri, 19 Apr 2013 12:38:30 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:51141 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030927Ab3DSQi1 (ORCPT ); Fri, 19 Apr 2013 12:38:27 -0400 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MLI001P5GVYD9R0@mailout4.samsung.com>; Sat, 20 Apr 2013 01:38:26 +0900 (KST) X-AuditID: cbfee61b-b7f076d0000034b6-e0-51717302f3e6 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 69.57.13494.20371715; Sat, 20 Apr 2013 01:38:26 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MLI007XRGVRC400@mmp2.samsung.com>; Sat, 20 Apr 2013 01:38:26 +0900 (KST) From: Lukasz Majewski To: Kukjin Kim Cc: Mike Turquette , Zhang Rui , devicetree-discuss@lists.ozlabs.org, linux-samsung-soc@vger.kernel.org, Linux PM list , Amit Daniel Kachhap , Lukasz Majewski , Kyungmin Park Subject: [PATCH 1/6] clk:exynos4:TMU Thermal Measurement Unit clock added to common clock framework Date: Fri, 19 Apr 2013 18:38:08 +0200 Message-id: <1366389493-8239-2-git-send-email-l.majewski@samsung.com> X-Mailer: git-send-email 1.7.10 In-reply-to: <1366389493-8239-1-git-send-email-l.majewski@samsung.com> References: <1366389493-8239-1-git-send-email-l.majewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHLMWRmVeSWpSXmKPExsVy+t9jQV2m4sJAg1PrpC2WPJjCaHFg9kNW i94FV9kszja9Ybd483Azo8Xn3iOMFjPO72OyeDrhIpvFk4d9bA6cHov3vGTyuHNtD5vH+RkL GT36tqxi9Pi8SS6ANYrLJiU1J7MstUjfLoEr42K3RMEW0Yrn/WfZGxh/CHYxcnJICJhIHHra zAhhi0lcuLeerYuRi0NIYDqjxNTpDUwQTheTxM7165hAqtgE9CQ+330KZosIqEn0LN7KCFLE LHCaSWLi66WsIAlhgVSJx7PesYPYLAKqEu9/bwWL8wq4Skxb+pINYp28xNP7fWA2p4CbxL8Z LWBnCAHVdD89zjyBkXcBI8MqRtHUguSC4qT0XCO94sTc4tK8dL3k/NxNjOBQeya9g3FVg8Uh RgEORiUe3g/RhYFCrIllxZW5hxglOJiVRHiXmwGFeFMSK6tSi/Lji0pzUosPMUpzsCiJ8x5s tQ4UEkhPLEnNTk0tSC2CyTJxcEo1MPY/djo3L2ufB/v1/cvveTy4tGI5x98XKzNttI7xxSze aXbh7NL+BJGVS7KebVo6bfo+69kPWsV33bVJCXsrWXCw7ULQtBm/+Q5qfnuueDVbzOTGeruQ xG9rT/rUKsx+M8uneHaRZl62yr0rzLlPPnFu9heQ2Ri57vzxuA9SNsct27QyzKps9YKVWIoz Eg21mIuKEwEKYgyhMQIAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org TMU is now supported with a exynos4 common clock framework. "tmu_apbif" clock has been defined with a common clock framework. Signed-off-by: Lukasz Majewski Signed-off-by: Kyungmin Park Cc: Mike Turquette --- Documentation/devicetree/bindings/clock/exynos4-clock.txt | 1 + drivers/clk/samsung/clk-exynos4.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt index ea5e26f..9afe6cb 100644 --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos4-clock.txt @@ -235,6 +235,7 @@ Exynos4 SoC and this is specified where applicable. spi0_isp_sclk 380 Exynos4x12 spi1_isp_sclk 381 Exynos4x12 uart_isp_sclk 382 Exynos4x12 + tmu_apbif 383 [Mux Clocks] diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 7104669..66c4ce4 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -170,7 +170,7 @@ enum exynos4_clks { gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp, mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp, asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk, - spi1_isp_sclk, uart_isp_sclk, + spi1_isp_sclk, uart_isp_sclk, tmu_apbif, /* mux clocks */ mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, @@ -807,6 +807,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"), GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"), GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"), + GATE_A(tmu_apbif, "tmu_apbif", "aclk100", + E4210_GATE_IP_PERIR, 17, 0, 0, "tmu_apbif"), GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), }; @@ -834,6 +836,8 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"), GATE_A(keyif, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"), + GATE_A(tmu_apbif, "tmu_apbif", "aclk100", + E4X12_GATE_IP_PERIR, 17, 0, 0, "tmu_apbif"), GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp", E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre",