From patchwork Fri May 17 05:55:52 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 2581161 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 8888FE00E5 for ; Fri, 17 May 2013 06:09:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754663Ab3EQGJ3 (ORCPT ); Fri, 17 May 2013 02:09:29 -0400 Received: from mail-pd0-f176.google.com ([209.85.192.176]:60633 "EHLO mail-pd0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754451Ab3EQGJZ (ORCPT ); Fri, 17 May 2013 02:09:25 -0400 Received: by mail-pd0-f176.google.com with SMTP id x10so3024655pdj.35 for ; Thu, 16 May 2013 23:09:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references:x-gm-message-state; bh=WrStDPyT/UPnZGMOOeL1gzjXLxSsghEcO9SdoVs0t74=; b=pJLhAgoHeS/Mnf+KmBaisdI8QCc+Vg/+nDGQTOrTaj0xNB2hDbqJ++mM/XbuTdN1uo WP3zCFVnzIBaiiUnWI/7GVoncSFdZounxdtdwa0f/+xrSqMbfY5Pj7KaTZwUNomcTwPb /8PBhqPitVhomXnPYW8kcMmrgI3thP9Az3ZXncRSRu40TuitqB5tXg1CrHxcNaqHG5SH 2wH8M5W1xk2AOm8EXbL7o4ynwVIqqSO8IrDMNntK989PRafh/7JJZDegWv2ikGQfGKgF vofZHOAKZxrhDTM0YHj5BkchmggeUhREf/MSXLIGxDWVO6QtbNsdgtxJJx8LVfXccZ9U RIsA== X-Received: by 10.68.217.135 with SMTP id oy7mr47084545pbc.133.1368770965339; Thu, 16 May 2013 23:09:25 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id t1sm10802497pab.12.2013.05.16.23.09.22 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 16 May 2013 23:09:24 -0700 (PDT) From: Tushar Behera To: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, mturquette@linaro.org, thomas.abraham@linaro.org, patches@linaro.org Subject: [PATCH 1/2] clk: exynos5250: Update cpufreq related clocks for EXYNOS5250 Date: Fri, 17 May 2013 11:25:52 +0530 Message-Id: <1368770153-29041-2-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1368770153-29041-1-git-send-email-tushar.behera@linaro.org> References: <1368770153-29041-1-git-send-email-tushar.behera@linaro.org> X-Gm-Message-State: ALoCoQkZ0u7pt2OpEhvt6xja0uVigzOb5tM9tpBqUKyPyNinwoJH8FMpYNeSm9EmOf0Mambrdqtl Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera --- drivers/clk/samsung/clk-exynos5250.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 5c97e75..05d099d 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -208,10 +208,10 @@ struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { }; struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { - MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), - MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), + MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"), + MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), - MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1), + MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),