From patchwork Wed May 29 13:37:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas C Sajjan X-Patchwork-Id: 2629781 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 088A5DFE76 for ; Wed, 29 May 2013 13:38:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966207Ab3E2Nil (ORCPT ); Wed, 29 May 2013 09:38:41 -0400 Received: from mail-pd0-f182.google.com ([209.85.192.182]:41318 "EHLO mail-pd0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966078Ab3E2Nij (ORCPT ); Wed, 29 May 2013 09:38:39 -0400 Received: by mail-pd0-f182.google.com with SMTP id g10so8898297pdj.27 for ; Wed, 29 May 2013 06:38:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=XRs1BAUEVRn2e8NsmlsDjiHRh/r/fnECL9s4OZEsFUk=; b=BnAdiLrMEiTxLctZPid1Lapw074NcQFkujro9ldp4iJpRvNoGkyauuW/dxtZxzgGhU aJpq3tvH6Z4aRQeo1QNk1RdoyIKxkDuzr0rSM5rX8p2umP/hpaQQ12PLBXjd/DGPIDSg DSCT+F6EwP0FO1858a2pQsMHKZ4Sn69XyGBZS/R/cxmnCG4MdVQAtsmdcl8IQRLFK2LM /pvnfywCf7+eILC45achWY4HITuoX6H5pO6jwrh+78bGs3iPCCnNBR3LPEXquPfrtiI2 waXqOKCnG5F7aK3/g6prLlnTioQbrnDdJ7xfpQpdTN06/BQNw46IqQiB0S249vPe3Y7G 7prw== X-Received: by 10.66.251.101 with SMTP id zj5mr3424056pac.122.1369834718772; Wed, 29 May 2013 06:38:38 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id b7sm37356944pba.39.2013.05.29.06.38.33 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 29 May 2013 06:38:37 -0700 (PDT) From: Vikas Sajjan To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, t.figa@samsung.com, yadi.brar01@gmail.com, dianders@chromium.org, mturquette@linaro.org, linux-arm-kernel@lists.infradead.org, thomas.abraham@linaro.org, patches@linaro.org, linaro-kernel@lists.linaro.org Subject: [PATCH v2 4/5] clk: samsung: Add set_rate() clk_ops for PLL36xx Date: Wed, 29 May 2013 19:07:56 +0530 Message-Id: <1369834677-20312-5-git-send-email-vikas.sajjan@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org> References: <1369834677-20312-1-git-send-email-vikas.sajjan@linaro.org> X-Gm-Message-State: ALoCoQkfYAWRUPyT6pR5hbhHwlW/ziyy7E8DcrRq62oRfRzlL5iUCe7b7Sy4d4xtfR7ETmdCgaIQ Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch adds set_rate and round_rate clk_ops for PLL36xx Signed-off-by: Vikas Sajjan Reviewed-by: Doug Anderson --- drivers/clk/samsung/clk-pll.c | 59 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 1fba7ef..3872161 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -210,6 +210,9 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name, #define PLL36XX_CON0_OFFSET 0x100 #define PLL36XX_CON1_OFFSET 0x104 +/* Maximum lock time can be 3000 * PDIV cycles */ +#define PLL36XX_LOCK_FACTOR 3000 + #define PLL36XX_KDIV_MASK (0xFFFF) #define PLL36XX_MDIV_MASK (0x1FF) #define PLL36XX_PDIV_MASK (0x3F) @@ -217,6 +220,8 @@ struct clk * __init samsung_clk_register_pll35xx(const char *name, #define PLL36XX_MDIV_SHIFT (16) #define PLL36XX_PDIV_SHIFT (8) #define PLL36XX_SDIV_SHIFT (0) +#define PLL36XX_KDIV_SHIFT (0) +#define PLL36XX_LOCK_STAT_SHIFT (29) static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -239,8 +244,57 @@ static unsigned long samsung_pll36xx_recalc_rate(struct clk_hw *hw, return (unsigned long)fvco; } +static int samsung_pll36xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 tmp, pll_con0, pll_con1; + const struct samsung_pll_rate_table *rate; + + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + pll_con0 = pll_readl(pll, PLL36XX_CON0_OFFSET); + pll_con1 = pll_readl(pll, PLL36XX_CON1_OFFSET); + + /* Set PLL lock time. */ + pll_writel(pll, (rate->pdiv * PLL36XX_LOCK_FACTOR), + PLL36XX_LOCK_OFFSET); + + /* Change PLL PMS values */ + pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | + (PLL36XX_PDIV_MASK << PLL36XX_PDIV_SHIFT) | + (PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT)); + pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | + (rate->pdiv << PLL36XX_PDIV_SHIFT) | + (rate->sdiv << PLL36XX_SDIV_SHIFT); + pll_writel(pll, pll_con0, PLL36XX_CON0_OFFSET); + + pll_con1 &= ~(PLL36XX_KDIV_MASK << PLL36XX_KDIV_SHIFT); + pll_con1 |= rate->kdiv << PLL36XX_KDIV_SHIFT; + pll_writel(pll, pll_con1, PLL36XX_CON1_OFFSET); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = pll_readl(pll, PLL36XX_CON0_OFFSET); + } while (!(tmp & (1 << PLL36XX_LOCK_STAT_SHIFT))); + + return 0; +} + static const struct clk_ops samsung_pll36xx_clk_ops = { .recalc_rate = samsung_pll36xx_recalc_rate, + .set_rate = samsung_pll36xx_set_rate, + .round_rate = samsung_pll_round_rate, +}; + +static const struct clk_ops samsung_pll36xx_clk_min_ops = { + .recalc_rate = samsung_pll36xx_recalc_rate, }; struct clk * __init samsung_clk_register_pll36xx(const char *name, @@ -264,6 +318,11 @@ struct clk * __init samsung_clk_register_pll36xx(const char *name, init.parent_names = &pname; init.num_parents = 1; + if (rate_table && rate_count) + init.ops = &samsung_pll36xx_clk_ops; + else + init.ops = &samsung_pll36xx_clk_min_ops; + pll->hw.init = &init; pll->base = base; pll->rate_table = rate_table;