| Message ID | 1370003496-19288-6-git-send-email-vikas.sajjan@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
Vikas and Yadwinder, On Fri, May 31, 2013 at 5:31 AM, Vikas Sajjan <vikas.sajjan@linaro.org> wrote: > While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the > "fout_vpll" (child), we found get rate was failing. > > So this patch moves the mout_vpllsrc MUX out of the existing common list > and registers the mout_vpllsrc MUX before the PLL registrations. > Its also adds the alias for the mout_vpllsrc MUX. I think the moving makes sense, but not the alias. IMHO global aliases should be avoided unless they can be strongly justified. In part 6 of this series I see where you're using the alias but I don't think you need it. In your case you are a clock provider, so I think you can use __clk_lookup("mout_vpllsrc") to find your clock. I will post an update on our gerrit and you can see what you think. If someone on the list thinks that using __clk_lookup() is a bad idea and they'd rather see the global alias, please shout. -Doug -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index ddf10ca..b0e6680 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -207,6 +207,11 @@ struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { FFACTOR(none, "fout_bplldiv2", "fout_bpll", 1, 2, 0), }; +struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { + MUX_A(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1, + "mout_vpllsrc"), +}; + struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), MUX(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1), @@ -214,7 +219,6 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1), MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), - MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1), MUX(none, "sclk_vpll", mout_vpll_p, SRC_TOP2, 16, 1), MUX(none, "sclk_epll", mout_epll_p, SRC_TOP2, 12, 1), MUX(none, "sclk_cpll", mout_cpll_p, SRC_TOP2, 8, 1), @@ -490,6 +494,9 @@ void __init exynos5250_clk_init(struct device_node *np) ARRAY_SIZE(exynos5250_fixed_rate_ext_clks), ext_clk_match); + samsung_clk_register_mux(exynos5250_pll_pmux_clks, + ARRAY_SIZE(exynos5250_pll_pmux_clks)); + apll = samsung_clk_register_pll35xx("fout_apll", "fin_pll", reg_base, NULL, 0); mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll",