From patchwork Thu Jun 6 11:22:28 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 2679641 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id B55DFDF23A for ; Thu, 6 Jun 2013 11:37:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932946Ab3FFLg5 (ORCPT ); Thu, 6 Jun 2013 07:36:57 -0400 Received: from mail-pd0-f169.google.com ([209.85.192.169]:55531 "EHLO mail-pd0-f169.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932374Ab3FFLgz (ORCPT ); Thu, 6 Jun 2013 07:36:55 -0400 Received: by mail-pd0-f169.google.com with SMTP id y10so3245593pdj.14 for ; Thu, 06 Jun 2013 04:36:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=7kfvxHlz3of2T72Mwq6wrnN9VwqprgeWcr8ja+YCC3o=; b=DTmuvztjLP8guFHjvCfDOVbtC6k021k3JQVCiV5Zvco582dqso47iRfm48yjwemS65 +awb3oTTE26pmPqUOpL8j3wcgBC9OHSLqolj3m3VHwu7689c8manVM+wAJ/erHOLhrRq yqDKyK+sEvKn2hNVARjkSMQtrrURdm6bjT82DBn0QLZWR7bk8S2yt9++rR2n6QBq824P wCDq27daKuv8uqnVpkNnUCjNnD1BENKsPfh060ThNdQdoLgOqEKS0uujcnKu9XeEOwNH Eokt45idll/A/1nglHuoK57QRiEv4RT0XleBJtGGvb3o8xcDqqu7D/HMZwqVAYLQS74i GcQQ== X-Received: by 10.66.122.68 with SMTP id lq4mr38099017pab.78.1370518615455; Thu, 06 Jun 2013 04:36:55 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id dr6sm77362405pac.11.2013.06.06.04.36.51 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Jun 2013 04:36:54 -0700 (PDT) From: Tushar Behera To: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, patches@linaro.org Subject: [PATCH 2/2] clk: exynos4: Add alias for cpufreq related clocks Date: Thu, 6 Jun 2013 16:52:28 +0530 Message-Id: <1370517749-29892-3-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1370517749-29892-1-git-send-email-tushar.behera@linaro.org> References: <1370517749-29892-1-git-send-email-tushar.behera@linaro.org> X-Gm-Message-State: ALoCoQkmV5QmXaulFZLEV8QJXDKQOWTEXBl0pUkQxhkf0yz8kJmohcp7rS0rxm/gpO8dnASfqH/1 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org cpufreq driver for EXYNOS4 based SoCs are not platform drivers, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. 'armclk', 'moutcore', 'mout_mpll' and 'mout_apll' clock aliases are defined. Signed-off-by: Tushar Behera --- drivers/clk/samsung/clk-exynos4.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 3c1f888..1e4258a 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -356,8 +356,8 @@ struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { /* list of mux clocks supported in all exynos4 soc's */ struct samsung_mux_clock exynos4_mux_clks[] __initdata = { - MUX_F(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, - CLK_SET_RATE_PARENT, 0), + MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0, "mout_apll"), MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), @@ -385,9 +385,9 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), - MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"), + MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "mout_mpll"), MUX_A(mout_core, "mout_core", mout_core_p4210, - SRC_CPU, 16, 1, "mout_core"), + SRC_CPU, 16, 1, "moutcore"), MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1, "sclk_vpll"), MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), @@ -534,7 +534,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = { DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), - DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "arm_clk"), + DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "armclk"), DIV_A(sclk_apll, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, "sclk_apll"), DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4,