From patchwork Mon Jun 10 11:01:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2696851 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 4ADE43FD4E for ; Mon, 10 Jun 2013 10:42:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751862Ab3FJKmJ (ORCPT ); Mon, 10 Jun 2013 06:42:09 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:9400 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751843Ab3FJKmI (ORCPT ); Mon, 10 Jun 2013 06:42:08 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MO600GPOB275SJ0@mailout4.samsung.com> for linux-samsung-soc@vger.kernel.org; Mon, 10 Jun 2013 19:42:07 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 61.33.08825.F7DA5B15; Mon, 10 Jun 2013 19:42:07 +0900 (KST) X-AuditID: cbfee68e-b7f276d000002279-d5-51b5ad7ff4ed Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id BF.FF.21068.F7DA5B15; Mon, 10 Jun 2013 19:42:07 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MO6001FHATOFA30@mmp2.samsung.com>; Mon, 10 Jun 2013 19:42:07 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org Cc: dri-devel@lists.freedesktop.org, kgene.kim@samsung.com, sw0312.kim@samsung.com, inki.dae@samsung.com, joshi@samsung.com, arun.kk@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH 4/5] clk/exynos5250: add clock for tv sysmmu Date: Mon, 10 Jun 2013 16:31:01 +0530 Message-id: <1370862062-16680-5-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1370862062-16680-1-git-send-email-rahul.sharma@samsung.com> References: <1370862062-16680-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmplkeLIzCtJLcpLzFFi42JZI2JSo1u/dmugwanf6hYfT91mtTgw+yGr xZWv79ksJt2fwGLxfdcXdoveBVfZLGac38dksfBFvMWURYdZLWZMfsnmwOWxc9Zddo/73ceZ PM7PWMjo0bdlFaPH501yAaxRXDYpqTmZZalF+nYJXBl/5j1lLfgiWbHh+0fGBsYHol2MnBwS AiYS3csWsUDYYhIX7q1n62Lk4hASWMoo8fz5ciaYovY9F8CKhASmM0pcXKMFUTSbSWLXlyNg RWwCuhKzDz5jBLFFBLwkutdsZwcpYha4wihx7fAtsCJhARuJgy/7wWwWAVWJJbuPgzXwCnhI POqYxwyxTVGi+9kENhCbU8BT4sSsQ4wQmz0k/uzdywwyVEJgE7tE47sVbBCDBCS+TT4EdB4H UEJWYtMBqDmSEgdX3GCZwCi8gJFhFaNoakFyQXFSepGRXnFibnFpXrpecn7uJkZgFJz+96xv B+PNA9aHGJOBxk1klhJNzgdGUV5JvKGxmZGFqYmpsZG5pRlpwkrivGot1oFCAumJJanZqakF qUXxRaU5qcWHGJk4OKUaGGWv2kxO1bpU2BC6d+PH4r6iE05NjBIbH2yZsvtIa2HAsWtxQa0M fQL996zb3u1se50fMvNe1o/breVhJ41nfOzx1vjzKkhXe4qFTbTWsy9Pzy3+9OPrQo64oP3s qRuTHGdtOz/3maaxQ7T79AiDqc7MfEkp0zIYtq465+d1bXoHd+ra8AknHyixFGckGmoxFxUn AgBfKcplmAIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEIsWRmVeSWpSXmKPExsVy+t9jQd36tVsDDd73y1l8PHWb1eLA7Ies Fle+vmezmHR/AovF911f2C16F1xls5hxfh+TxcIX8RZTFh1mtZgx+SWbA5fHzll32T3udx9n 8jg/YyGjR9+WVYwenzfJBbBGNTDaZKQmpqQWKaTmJeenZOal2yp5B8c7x5uaGRjqGlpamCsp 5CXmptoqufgE6Lpl5gBdpaRQlphTChQKSCwuVtK3wzQhNMRN1wKmMULXNyQIrsfIAA0krGHM +DPvKWvBF8mKDd8/MjYwPhDtYuTkkBAwkWjfc4EFwhaTuHBvPRuILSQwnVHi4hqtLkYuIHs2 k8SuL0eYQBJsAroSsw8+YwSxRQS8JLrXbGcHKWIWuMIoce3wLbAiYQEbiYMv+8FsFgFViSW7 j4M18Ap4SDzqmMcMsU1RovvZBLBtnAKeEidmHWKE2Owh8WfvXuYJjLwLGBlWMYqmFiQXFCel 5xrpFSfmFpfmpesl5+duYgTH2DPpHYyrGiwOMQpwMCrx8D74tSVQiDWxrLgy9xCjBAezkghv 8aytgUK8KYmVValF+fFFpTmpxYcYk4GumsgsJZqcD4z/vJJ4Q2MTc1NjU0sTCxMzS9KElcR5 D7ZaBwoJpCeWpGanphakFsFsYeLglGpgnCdV4WX0N/rTwTVJMpFXmepPbJqWs+3wg1u9N5by nY41W3unVGlb9CaOs8LbTVum/NXTD73X5Xb3q2yM+Mmfi85G7XWzDL16d+6Bec1KNve2rP3z 4NTsg8qHrxgfM/8/u+hK38XIDUbXHuRYmTLs6V/j3/Kby9MjwFm3zMT/9uEi9+98xlZdc5RY ijMSDbWYi4oTAVGWxZf1AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Adding sysmmu clock for tv for exynos5250 SoC. It also adds aclk200_disp1 mux which is the actual parent of the disp1 block (contains hdmi, mixer, sysmmu_tv). Signed-off-by: Rahul Sharma --- Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 + drivers/clk/samsung/clk-exynos5250.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index f333d61..f1c7e7f 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -156,6 +156,7 @@ clock which they consume. dp 342 mixer 343 hdmi 344 + smmu_tv 345 [Clock Muxes] diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 88cdb13..bb93d61 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -24,6 +24,7 @@ #define SRC_CORE1 0x4204 #define SRC_TOP0 0x10210 #define SRC_TOP2 0x10218 +#define SRC_TOP3 0x1021C #define SRC_GSCL 0x10220 #define SRC_DISP1_0 0x1022c #define SRC_MAU 0x10240 @@ -99,7 +100,7 @@ enum exynos5250_clks { spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2, hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct, - wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, + wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, smmu_tv, /* mux clocks */ mout_hdmi = 1024, @@ -172,6 +173,7 @@ PNAME(mout_mpll_user_p) = { "fin_pll", "sclk_mpll" }; PNAME(mout_bpll_user_p) = { "fin_pll", "sclk_bpll" }; PNAME(mout_aclk166_p) = { "sclk_cpll", "sclk_mpll_user" }; PNAME(mout_aclk200_p) = { "sclk_mpll_user", "sclk_bpll_user" }; +PNAME(mout_aclk200_disp1_sub_p) = { "fin_pll", "aclk200" }; PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; PNAME(mout_usb3_p) = { "sclk_mpll_user", "sclk_cpll" }; PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", @@ -227,6 +229,7 @@ struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX(none, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), MUX(none, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), MUX(none, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), + MUX(none, "aclk200_disp1", mout_aclk200_disp1_sub_p, SRC_TOP3, 4, 1), MUX(none, "mout_cam_bayer", mout_group1_p, SRC_GSCL, 12, 4), MUX(none, "mout_cam0", mout_group1_p, SRC_GSCL, 16, 4), MUX(none, "mout_cam1", mout_group1_p, SRC_GSCL, 20, 4), @@ -328,6 +331,7 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(smmu_gscl1, "smmu_gscl1", "aclk266", GATE_IP_GSCL, 8, 0, 0), GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0), GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0), + GATE(smmu_tv, "smmu_tv", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0), GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0),