From patchwork Tue Jun 18 14:33:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2742631 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 33BE6C0AB1 for ; Tue, 18 Jun 2013 14:09:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 149F32040C for ; Tue, 18 Jun 2013 14:09:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D778A20384 for ; Tue, 18 Jun 2013 14:09:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932879Ab3FROJw (ORCPT ); Tue, 18 Jun 2013 10:09:52 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:51136 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932855Ab3FROJw (ORCPT ); Tue, 18 Jun 2013 10:09:52 -0400 Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOL00175E07N890@mailout3.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 18 Jun 2013 23:09:51 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.125]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 96.15.08825.F2A60C15; Tue, 18 Jun 2013 23:09:51 +0900 (KST) X-AuditID: cbfee68e-b7f276d000002279-d7-51c06a2f3ba2 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 9A.7F.28381.E2A60C15; Tue, 18 Jun 2013 23:09:51 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOL00G19DZTS050@mmp1.samsung.com>; Tue, 18 Jun 2013 23:09:50 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, dri-devel@lists.freedesktop.org Cc: kgene.kim@samsung.com, sw0312.kim@samsung.com, inki.dae@samsung.com, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH 4/5] clk/exynos5420: add hdmi mux to change parents in hdmi driver Date: Tue, 18 Jun 2013 20:03:17 +0530 Message-id: <1371565998-3642-5-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1371565998-3642-1-git-send-email-rahul.sharma@samsung.com> References: <1371565998-3642-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42JZI2JSq6ufdSDQYNEHHosDsx+yWlz5+p7N YtL9CSwW33d9YbfoXXCVzWLG+X1MFgtfxFtMWXSY1WLG5JdsDpweO2fdZfe4332cyeP8jIWM Hn1bVjF6fN4kF8AaxWWTkpqTWZZapG+XwJWx41ZcwQz+ip3NZxgbGE/wdDFyckgImEiset3A CGGLSVy4t56ti5GLQ0hgKaPEgRdd7DBFcw+8Z4RILGKUWLjiGVTVbCaJHxsms4FUsQnoSsw+ +AxslIhArkTD33YWkCJmgVmMEt9nnwEbJSwQIrGn6RQriM0ioCpxrekhE4jNK+Au8e7xSmaI dYoS3c8mgA3lFPCQOHf/Bli9EFDNzM7fYJslBFaxS1x408YGMUhA4tvkQ0DbOIASshKbDkDN kZQ4uOIGywRG4QWMDKsYRVMLkguKk9KLjPSKE3OLS/PS9ZLzczcxAkP/9L9nfTsYbx6wPsSY DDRuIrOUaHI+MHbySuINjc2MLExNTI2NzC3NSBNWEudVa7EOFBJITyxJzU5NLUgtii8qzUkt PsTIxMEp1cA4Z/7tzP/33yR+aJ6V3DXH5nSwyTtho3SFuVuN10nH3xHb+atO4/O5+lnB3xrc 4l+e1CoPCTbYxi1jWM4rIvD4jgVDnPmnvXM3frAR6LP5p+Pkc0V/TknfssYi31tCfLwZvG73 f0Rk7zfd5XBJLGWT7V/vCmFxy2kRJy6on1FOtOGfdKVa9rASS3FGoqEWc1FxIgDd2QtIkwIA AA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLIsWRmVeSWpSXmKPExsVy+t9jAV39rAOBBrNPsFgcmP2Q1eLK1/ds FpPuT2Cx+L7rC7tF74KrbBYzzu9jslj4It5iyqLDrBYzJr9kc+D02DnrLrvH/e7jTB7nZyxk 9OjbsorR4/MmuQDWqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRb JRefAF23zBygg5QUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGTtuxRXM 4K/Y2XyGsYHxBE8XIyeHhICJxNwD7xkhbDGJC/fWs3UxcnEICSxilFi44hmUM5tJ4seGyWwg VWwCuhKzDz4D6xARyJVo+NvOAlLELDCLUeL77DPsIAlhgRCJPU2nWEFsFgFViWtND5lAbF4B d4l3j1cyQ6xTlOh+NgFsKKeAh8S5+zfA6oWAamZ2/mabwMi7gJFhFaNoakFyQXFSeq6hXnFi bnFpXrpecn7uJkZwZD2T2sG4ssHiEKMAB6MSD2+C2P5AIdbEsuLK3EOMEhzMSiK8CokHAoV4 UxIrq1KL8uOLSnNSiw8xJgNdNZFZSjQ5Hxj1eSXxhsYm5qbGppYmFiZmlqQJK4nzHmi1DhQS SE8sSc1OTS1ILYLZwsTBKdXAaCqbq1Z+7/JFg2W2SxT4D1dEnJ+n6blPaVvY7sMFqfIZTKdf tVTZS6zYeuqgmWm2+tKayfONG7sY3CvnvtKvdN/AMXFx+8zzn765C7H2rdP/+tzgrxWjZJXP b4fpxT8OKa/Oz4k4duecc9UFrvauCr/S4Dd/jKbfYkyelCmuaP3Nw+B+dFipEktxRqKhFnNR cSIAQPA+e/ACAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP hdmi driver needs to change the parent of hdmi clock to pixel clock or hdmiphy clock, based on the stability of hdmiphy. This patch is exposing the mux for changing the parent. Signed-off-by: Rahul Sharma --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 5 +++++ drivers/clk/samsung/clk-exynos5420.c | 5 ++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index f0b1ce0..c7a319d 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -182,6 +182,11 @@ clock which they consume. g3d 501 smmu_tv 502 + Mux ID + ---------------------------- + + mout_hdmi 1024 + Example 1: An example of a clock controller node is listed below. clock: clock-controller@0x10010000 { diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 193d25e..59cf177 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -111,6 +111,9 @@ enum exynos5420_clks { aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0, smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_tv, + /* mux clocks */ + mout_hdmi = 1024, + nr_clks, }; @@ -371,7 +374,7 @@ struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3), MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3), MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3), - MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), + MUX(mout_hdmi, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1), /* MAU Block */ MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),