| Message ID | 1371565998-3642-6-git-send-email-rahul.sharma@samsung.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
With this patch, it is at par with Exynos5250 and Exynos4 clocks where sclk_pixel ID is assigned to a divider clock but in real, sclk_pixel is listed under gate clocks (enum value). Alternate to this, I can allocate a new ID, div_pixel, listed under new category of Divider Clocks for Exyno4, 5250 and 5420. div_pixel ID can be assigned to pixel clock dividers for all 3 SoCs. This ID can be accessed by hdmi driver as usual. While sclk_pixel ID can be left unused for Exyno4, 5250 as there are no pixel clock gates. And, For 5420, sclk_pixel can optionally be used to enable/disable the pixel clock gate. Regards, Rahul Sharma. On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma <rahul.sharma@samsung.com> wrote: > sclk_pixel is used to represent pixel clock divider on all exynos > SoCs not as a gate clock. It is queried in driver to pass as the > parent to hdmi clock while switching between parents. A new ID can > be asssigned Pixel gate clock which is currently not in use. Pixel > clock gate is default 'on'. > > Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> > --- > drivers/clk/samsung/clk-exynos5420.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c > index 59cf177..edd0696 100644 > --- a/drivers/clk/samsung/clk-exynos5420.c > +++ b/drivers/clk/samsung/clk-exynos5420.c > @@ -434,7 +434,7 @@ struct samsung_div_clock exynos5420_div_clks[] __initdata = { > DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), > DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), > DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), > - DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), > + DIV(sclk_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), > > /* Audio Block */ > DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), > @@ -570,7 +570,7 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { > GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), > GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", > GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), > - GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", > + GATE(none, "sclk_pixel", "dout_hdmi_pixel", > GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), > GATE(sclk_dp1, "sclk_dp1", "dout_dp1", > GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), > -- > 1.7.10.4 > -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
+Mike On Tue, Jun 18, 2013 at 7:54 PM, Rahul Sharma <r.sh.open@gmail.com> wrote: > With this patch, it is at par with Exynos5250 and Exynos4 clocks > where sclk_pixel ID is assigned to a divider clock but in real, > sclk_pixel is listed under gate clocks (enum value). > > Alternate to this, I can allocate a new ID, div_pixel, listed under > new category of Divider Clocks for Exyno4, 5250 and 5420. > div_pixel ID can be assigned to pixel clock dividers for all 3 SoCs. > This ID can be accessed by hdmi driver as usual. While sclk_pixel > ID can be left unused for Exyno4, 5250 as there are no pixel clock > gates. And, For 5420, sclk_pixel can optionally be used to > enable/disable the pixel clock gate. > > Regards, > Rahul Sharma. > > On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma <rahul.sharma@samsung.com> wrote: >> sclk_pixel is used to represent pixel clock divider on all exynos >> SoCs not as a gate clock. It is queried in driver to pass as the >> parent to hdmi clock while switching between parents. A new ID can >> be asssigned Pixel gate clock which is currently not in use. Pixel >> clock gate is default 'on'. >> >> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> >> --- >> drivers/clk/samsung/clk-exynos5420.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c >> index 59cf177..edd0696 100644 >> --- a/drivers/clk/samsung/clk-exynos5420.c >> +++ b/drivers/clk/samsung/clk-exynos5420.c >> @@ -434,7 +434,7 @@ struct samsung_div_clock exynos5420_div_clks[] __initdata = { >> DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), >> DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), >> DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), >> - DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), >> + DIV(sclk_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), >> >> /* Audio Block */ >> DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), >> @@ -570,7 +570,7 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { >> GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), >> GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", >> GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), >> - GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", >> + GATE(none, "sclk_pixel", "dout_hdmi_pixel", >> GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), >> GATE(sclk_dp1, "sclk_dp1", "dout_dp1", >> GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0), >> -- >> 1.7.10.4 >> -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 59cf177..edd0696 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -434,7 +434,7 @@ struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), - DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), + DIV(sclk_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), /* Audio Block */ DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), @@ -570,7 +570,7 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), - GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", + GATE(none, "sclk_pixel", "dout_hdmi_pixel", GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), GATE(sclk_dp1, "sclk_dp1", "dout_dp1", GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
sclk_pixel is used to represent pixel clock divider on all exynos SoCs not as a gate clock. It is queried in driver to pass as the parent to hdmi clock while switching between parents. A new ID can be asssigned Pixel gate clock which is currently not in use. Pixel clock gate is default 'on'. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> --- drivers/clk/samsung/clk-exynos5420.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)