From patchwork Tue Jun 18 14:33:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2742661 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6B81CC0AB1 for ; Tue, 18 Jun 2013 14:10:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4EB0020384 for ; Tue, 18 Jun 2013 14:09:59 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 12CD82040B for ; Tue, 18 Jun 2013 14:09:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932873Ab3FROJz (ORCPT ); Tue, 18 Jun 2013 10:09:55 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:40281 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932855Ab3FROJy (ORCPT ); Tue, 18 Jun 2013 10:09:54 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOL00MGDE09HUL0@mailout4.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 18 Jun 2013 23:09:53 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 5B.2A.29708.13A60C15; Tue, 18 Jun 2013 23:09:53 +0900 (KST) X-AuditID: cbfee690-b7f6f6d00000740c-f8-51c06a31239c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id B5.26.21068.13A60C15; Tue, 18 Jun 2013 23:09:53 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOL00G19DZTS050@mmp1.samsung.com>; Tue, 18 Jun 2013 23:09:53 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, dri-devel@lists.freedesktop.org Cc: kgene.kim@samsung.com, sw0312.kim@samsung.com, inki.dae@samsung.com, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH 5/5] clk/exynos5420: assign sclk_pixel id to pixel clock divider Date: Tue, 18 Jun 2013 20:03:18 +0530 Message-id: <1371565998-3642-6-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1371565998-3642-1-git-send-email-rahul.sharma@samsung.com> References: <1371565998-3642-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgkeLIzCtJLcpLzFFi42JZI2JSpWuYdSDQ4MdsI4sDsx+yWlz5+p7N YtL9CSwW33d9YbfoXXCVzWLG+X1MFgtfxFtMWXSY1WLG5JdsDpweO2fdZfe4332cyeP8jIWM Hn1bVjF6fN4kF8AaxWWTkpqTWZZapG+XwJVxdPd5loK/PBVvd3xjb2Bs4e5i5OCQEDCRmPbe oIuRE8gUk7hwbz1bFyMXh5DAUkaJh5/fsUEkTCT+rW+BSixilOie3wjlzGaS2LbqBQtIFZuA rsTsg88YQWwRgVyJhr/tLCBFzAKzGCW+zz7DDpIQFgiQ6HjznxXEZhFQlXj26yVYA6+Au8Sn jz2MEOsUJbqfTQBbzSngIXHu/g2weiGgmpmdv8E2SwisYpdo3jGVBWKQgMS3yYdYIP6Rldh0 gBlijqTEwRU3WCYwCi9gZFjFKJpakFxQnJReZKJXnJhbXJqXrpecn7uJERj6p/89m7CD8d4B 60OMyUDjJjJLiSbnA2MnryTe0NjMyMLUxNTYyNzSjDRhJXFe9RbrQCGB9MSS1OzU1ILUovii 0pzU4kOMTBycUg2MAYe/re6UWbpVoZhd+USkabuOf7gD44nrU3qzRe8fEju86p7wbo6tboo5 3tXcUtI9bp5NOc37wrl37dERnHyEd4PN/WnBTZNezDys914mO2WdwP6bHw74yHzkKtNPWnvu 2ptDPZIGbYpmX/cdXShU8e3WjsrL15vy+zt334/Y16j9wqbacp2UEktxRqKhFnNRcSIAPyo8 hpMCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrHIsWRmVeSWpSXmKPExsVy+t9jAV3DrAOBBpuvqVscmP2Q1eLK1/ds FpPuT2Cx+L7rC7tF74KrbBYzzu9jslj4It5iyqLDrBYzJr9kc+D02DnrLrvH/e7jTB7nZyxk 9OjbsorR4/MmuQDWqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRb JRefAF23zBygg5QUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGUd3n2cp +MtT8XbHN/YGxhbuLkZODgkBE4l/61vYIGwxiQv31gPZXBxCAosYJbrnN0I5s5kktq16wQJS xSagKzH74DNGEFtEIFei4W87C0gRs8AsRonvs8+wgySEBQIkOt78ZwWxWQRUJZ79egnWwCvg LvHpYw8jxDpFie5nE8BWcwp4SJy7fwOsXgioZmbnb7YJjLwLGBlWMYqmFiQXFCel5xrpFSfm Fpfmpesl5+duYgTH1jPpHYyrGiwOMQpwMCrx8CaI7Q8UYk0sK67MPcQowcGsJMKrkHggUIg3 JbGyKrUoP76oNCe1+BBjMtBVE5mlRJPzgXGfVxJvaGxibmpsamliYWJmSZqwkjjvwVbrQCGB 9MSS1OzU1ILUIpgtTBycUg2M2ql/i0tEN2gvFvmtU2z3LHjN6fBnTC9Kb9z/tEi3QOmfiGTc t9PTMx/2L3pgx7xLp/2tKZcO98aELRvFX14P+1GStumftAP7roU2vhppyVkr7FYcfnc9qMqu rfPFq56vXHsVA8w29yX81zn8vcnFX2Lf3ISJBRPu+Qao30rT6Kz7pN5c0BegxFKckWioxVxU nAgAlycjhPECAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP sclk_pixel is used to represent pixel clock divider on all exynos SoCs not as a gate clock. It is queried in driver to pass as the parent to hdmi clock while switching between parents. A new ID can be asssigned Pixel gate clock which is currently not in use. Pixel clock gate is default 'on'. Signed-off-by: Rahul Sharma --- drivers/clk/samsung/clk-exynos5420.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 59cf177..edd0696 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -434,7 +434,7 @@ struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), - DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), + DIV(sclk_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), /* Audio Block */ DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), @@ -570,7 +570,7 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), - GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", + GATE(none, "sclk_pixel", "dout_hdmi_pixel", GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), GATE(sclk_dp1, "sclk_dp1", "dout_dp1", GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),