From patchwork Mon Jun 24 10:50:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kachhap X-Patchwork-Id: 2770451 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6F5A09F245 for ; Mon, 24 Jun 2013 10:58:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 72E48201DD for ; Mon, 24 Jun 2013 10:58:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 73C08201D9 for ; Mon, 24 Jun 2013 10:58:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752859Ab3FXKvp (ORCPT ); Mon, 24 Jun 2013 06:51:45 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:45560 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752738Ab3FXKvn (ORCPT ); Mon, 24 Jun 2013 06:51:43 -0400 Received: by mail-pa0-f50.google.com with SMTP id fb1so10809195pad.9 for ; Mon, 24 Jun 2013 03:51:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=TtP29eGf6Fg1mfAjoMO4zGtDcAz2uXva1iINDZSTe8I=; b=VVVa6XYnaa59Omghr0jgdxbJptuHdGYQzd30IqG7mBqV5A2pPAeW9yUhifjntD6gEW zYRkI+7Bp/WEIY6ArNX8yYhKr4sVg1U/yLOfsJWx0lqtrVE6bD1B4XnNT5i+7mYenNrV 5NtVmbp0lfIKz3XpCffcoiwnttLMRvIPBtYAn1nNlZk3d+2N17w/mmkacQM93X2ILNWc HHHFwt7052kFSMI6l7BGlgTrLLLtinhBbaTNVkrVw+0cKyfFgUtj5Q+TFdMOo0+JCu6s TfdpWHLVt4tSvQ1yBNlWgBzK1wtolt7ml2uCY8vaepSP0YTYd7dskwdB0IzfvRMLbKsI +2eg== X-Received: by 10.66.5.168 with SMTP id t8mr26751784pat.196.1372071103007; Mon, 24 Jun 2013 03:51:43 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id tq8sm17631973pbc.30.2013.06.24.03.51.39 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Mon, 24 Jun 2013 03:51:41 -0700 (PDT) From: Amit Daniel Kachhap To: linux-pm@vger.kernel.org, Zhang Rui , Eduardo Valentin Cc: linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, amit.kachhap@gmail.com, Kukjin Kim Subject: [PATCH V7 08/30] thermal: exynos: Add missing definations and code cleanup Date: Mon, 24 Jun 2013 16:20:29 +0530 Message-Id: <1372071051-3167-9-git-send-email-amit.daniel@samsung.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1372071051-3167-1-git-send-email-amit.daniel@samsung.com> References: <1372071051-3167-1-git-send-email-amit.daniel@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds some extra register bitfield definations and cleans up the code to prepare for moving register macros and definations inside the TMU data section. In this code cleanup the TMU enable bit is correctly used as bit0 and bit1 is taken care which is reserve bit. Acked-by: Kukjin Kim Acked-by: Jonghwa Lee Signed-off-by: Amit Daniel Kachhap Acked-by: Eduardo Valentin --- drivers/thermal/samsung/exynos_tmu.c | 62 +++++++++++++++++++++++++--------- 1 files changed, 46 insertions(+), 16 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 5df04a1..fa33a48 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -43,9 +43,12 @@ #define EXYNOS_TMU_TRIM_TEMP_MASK 0xff #define EXYNOS_TMU_GAIN_SHIFT 8 +#define EXYNOS_TMU_GAIN_MASK 0xf #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 -#define EXYNOS_TMU_CORE_ON 3 -#define EXYNOS_TMU_CORE_OFF 2 +#define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f +#define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf +#define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 +#define EXYNOS_TMU_CORE_EN_SHIFT 0 #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50 /* Exynos4210 specific registers */ @@ -63,6 +66,7 @@ #define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10 #define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100 #define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000 +#define EXYNOS4210_TMU_TRIG_LEVEL_MASK 0x1111 #define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111 /* Exynos5250 and Exynos4412 specific registers */ @@ -72,17 +76,30 @@ #define EXYNOS_EMUL_CON 0x80 #define EXYNOS_TRIMINFO_RELOAD 0x1 +#define EXYNOS_TRIMINFO_SHIFT 0x0 +#define EXYNOS_TMU_RISE_INT_MASK 0x111 +#define EXYNOS_TMU_RISE_INT_SHIFT 0 +#define EXYNOS_TMU_FALL_INT_MASK 0x111 +#define EXYNOS_TMU_FALL_INT_SHIFT 12 #define EXYNOS_TMU_CLEAR_RISE_INT 0x111 #define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12) -#define EXYNOS_MUX_ADDR_VALUE 6 -#define EXYNOS_MUX_ADDR_SHIFT 20 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 +#define EXYNOS_TMU_TRIP_MODE_MASK 0x7 + +#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 +#define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 +#define EXYNOS_TMU_INTEN_RISE2_SHIFT 8 +#define EXYNOS_TMU_INTEN_RISE3_SHIFT 12 +#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 +#define EXYNOS_TMU_INTEN_FALL1_SHIFT 20 +#define EXYNOS_TMU_INTEN_FALL2_SHIFT 24 #define EFUSE_MIN_VALUE 40 #define EFUSE_MAX_VALUE 100 #ifdef CONFIG_THERMAL_EMULATION #define EXYNOS_EMUL_TIME 0x57F0 +#define EXYNOS_EMUL_TIME_MASK 0xffff #define EXYNOS_EMUL_TIME_SHIFT 16 #define EXYNOS_EMUL_DATA_SHIFT 8 #define EXYNOS_EMUL_DATA_MASK 0xFF @@ -261,24 +278,37 @@ static void exynos_tmu_control(struct platform_device *pdev, bool on) mutex_lock(&data->lock); clk_enable(data->clk); - con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT | - pdata->gain << EXYNOS_TMU_GAIN_SHIFT; + con = readl(data->base + EXYNOS_TMU_REG_CONTROL); - if (data->soc == SOC_ARCH_EXYNOS) { - con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT; - con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT); + if (pdata->reference_voltage) { + con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << + EXYNOS_TMU_REF_VOLTAGE_SHIFT); + con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; + } + + if (pdata->gain) { + con &= ~(EXYNOS_TMU_GAIN_MASK << EXYNOS_TMU_GAIN_SHIFT); + con |= (pdata->gain << EXYNOS_TMU_GAIN_SHIFT); + } + + if (pdata->noise_cancel_mode) { + con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << + EXYNOS_TMU_TRIP_MODE_SHIFT); + con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT); } if (on) { - con |= EXYNOS_TMU_CORE_ON; - interrupt_en = pdata->trigger_level3_en << 12 | - pdata->trigger_level2_en << 8 | - pdata->trigger_level1_en << 4 | - pdata->trigger_level0_en; + con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); + interrupt_en = + pdata->trigger_level3_en << EXYNOS_TMU_INTEN_RISE3_SHIFT | + pdata->trigger_level2_en << EXYNOS_TMU_INTEN_RISE2_SHIFT | + pdata->trigger_level1_en << EXYNOS_TMU_INTEN_RISE1_SHIFT | + pdata->trigger_level0_en << EXYNOS_TMU_INTEN_RISE0_SHIFT; if (pdata->threshold_falling) - interrupt_en |= interrupt_en << 16; + interrupt_en |= + interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; } else { - con |= EXYNOS_TMU_CORE_OFF; + con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); interrupt_en = 0; /* Disable all interrupts */ } writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);