From patchwork Fri Jul 5 08:42:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sachin Kamat X-Patchwork-Id: 2824030 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B971C9F7D6 for ; Fri, 5 Jul 2013 08:58:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C811C20158 for ; Fri, 5 Jul 2013 08:58:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 9C9EC20153 for ; Fri, 5 Jul 2013 08:58:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757208Ab3GEI6A (ORCPT ); Fri, 5 Jul 2013 04:58:00 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:50492 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757205Ab3GEI57 (ORCPT ); Fri, 5 Jul 2013 04:57:59 -0400 Received: by mail-pa0-f49.google.com with SMTP id ld11so2037977pab.8 for ; Fri, 05 Jul 2013 01:57:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=HiKTZ/AzswF05xUs+XBhO7Y9EVkz70/TOKkWGoCRnK8=; b=kCcSNOdz/CSvKmT5WKiEfczTlNnQRhu1DFKynhUsdlOPEntpYIfch6mGpvywsq7hto o2BRPQJnTpjRuoqVNmgxW47wNPol3FUWDHAtmiKRZ0DairAVH6EprwCjcxXHVDBsc8Q/ OXmsgFTOYMqIH/b8f4dPBToOjv8LsvnqlsaEcfEdMqFXGAQ5p+7eGtNqG3X4bFtqgX9N izaPxqovlHgB4YAraCFkvuSbIKi61s22JtC5iBx90I4EFT0lC/94YLZSY6HQMUdC/4F2 PeJkKBolYNT64nku+S8TFZcUG16ZQkmZ4+ahrKPVaVlKbk2cGRVIaMm2QrVKLzClPlhL tTsw== X-Received: by 10.66.219.38 with SMTP id pl6mr10611570pac.59.1373014678694; Fri, 05 Jul 2013 01:57:58 -0700 (PDT) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id aj3sm7351050pad.8.2013.07.05.01.57.55 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 05 Jul 2013 01:57:58 -0700 (PDT) From: Sachin Kamat To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: devicetree-discuss@lists.ozlabs.org, kgene.kim@samsung.com, sachin.kamat@linaro.org, patches@linaro.org, mturquette@linaro.org, inki.dae@samsung.com Subject: [PATCH 1/3] clk: exynos5250: Add G2D gate clock Date: Fri, 5 Jul 2013 14:12:27 +0530 Message-Id: <1373013749-14530-1-git-send-email-sachin.kamat@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQkX9nVZKqtJFT4+AZDTYNjh46tbSGudsoderUNkHXxkPewgaouAvd67SKtL7Llj/hLhSA3F Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds gate clock for G2D IP for Exynos5250 SoC. Signed-off-by: Sachin Kamat Cc: Mike Turquette --- This patch depends on the following patch: http://thread.gmane.org/gmane.linux.kernel.samsung-soc/20581 --- .../devicetree/bindings/clock/exynos5250-clock.txt | 1 + drivers/clk/samsung/clk-exynos5250.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 1a05761..7e88242 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -155,6 +155,7 @@ clock which they consume. dp 342 mixer 343 hdmi 344 + g2d 345 Example 1: An example of a clock controller node is listed below. diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 6f767c5..3da0bdf 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -62,6 +62,7 @@ #define SRC_CDREX 0x20200 #define PLL_DIV2_SEL 0x20a24 #define GATE_IP_DISP1 0x10928 +#define GATE_IP_ACP 0x10000 /* * Let each supported clock get a unique id. This id is used to lookup the clock @@ -99,7 +100,7 @@ enum exynos5250_clks { spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2, hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct, - wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, + wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, nr_clks, }; @@ -152,6 +153,7 @@ static __initdata unsigned long exynos5250_clk_regs[] = { SRC_CDREX, PLL_DIV2_SEL, GATE_IP_DISP1, + GATE_IP_ACP, }; /* list of all parent clock list */ @@ -463,6 +465,7 @@ struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(dp, "dp", "aclk200", GATE_IP_DISP1, 4, 0, 0), GATE(mixer, "mixer", "aclk200", GATE_IP_DISP1, 5, 0, 0), GATE(hdmi, "hdmi", "aclk200", GATE_IP_DISP1, 6, 0, 0), + GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), }; static __initdata struct of_device_id ext_clk_match[] = {