From patchwork Tue Aug 6 08:34:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 2839247 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A7C60BF535 for ; Tue, 6 Aug 2013 08:35:34 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DD23A20166 for ; Tue, 6 Aug 2013 08:35:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2EFE020149 for ; Tue, 6 Aug 2013 08:35:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754134Ab3HFIfN (ORCPT ); Tue, 6 Aug 2013 04:35:13 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:38253 "EHLO mail-pb0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753834Ab3HFIfG (ORCPT ); Tue, 6 Aug 2013 04:35:06 -0400 Received: by mail-pb0-f45.google.com with SMTP id mc17so112724pbc.32 for ; Tue, 06 Aug 2013 01:35:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k9BgpPz0HfKMYzhDb6vxkcq9FNVSps+cJky/Uf8iv1s=; b=KeWCuVv1dg8I6Oe0nZfu90T720QWCtRFb8koH1eAU+3fVGwjbvFgB/o3fz9RJvc68t q1HDb1HyPAvV31yA2+dQUuZzFt+scQlfzD6pj5QrONGu0Exr2oab6lUqMmHmvS9dpUfK sjMkbe3DjlD1wDk+OEhObEtHOgZ1nT6eET1npq7CDbz6cHmarSI6OM/Y6dXNppo13akk hKW9LpN3YoruI11eO0ncok47sZdChAtrEueq/N625g+IJdK/nPDTSHaxmaxKCfGgp90K 9+yAaBdAWyJzLgw7zJkafIP9kFvFIVGP8S0ifGvEQoXxeHE05TkB/MmXkaThmiVcBI6y 1wGg== X-Gm-Message-State: ALoCoQlC8RzSTpLVagH+6S5SSczgjgPVKI/XFmGs+h6SyOqoMYfmylOZiEk3qrxk6qjco45z4avv X-Received: by 10.68.253.138 with SMTP id aa10mr314904pbd.24.1375778105443; Tue, 06 Aug 2013 01:35:05 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id wr9sm621435pbc.7.2013.08.06.01.35.02 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 06 Aug 2013 01:35:04 -0700 (PDT) From: Chander Kashyap To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, mturquette@linaro.org, thomas.abraham@linaro.org, Chander Kashyap Subject: [RFC PATCH 3/3] clk: Exynos5250: Add alternate parent name for mout_cpu Date: Tue, 6 Aug 2013 14:04:25 +0530 Message-Id: <1375778065-21808-4-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1375778065-21808-1-git-send-email-chander.kashyap@linaro.org> References: <1375778065-21808-1-git-send-email-chander.kashyap@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Temporary parent migration is required during cpu frequency scaling. Hence this patch adds support to supply alternate parent name for cpu clock i.e. "mout_cpu". Signed-off-by: Chander Kashyap --- drivers/clk/samsung/clk-exynos5250.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 6f767c5..bfd96ba 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -209,10 +209,14 @@ struct samsung_fixed_factor_clock exynos5250_fixed_factor_clks[] __initdata = { }; struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { - MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"), - MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), + MUX_FA(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + CLK_SET_RATE_PARENT, 0, "mout_apll", NULL), + MUX_FA(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, + CLK_SET_RATE_PARENT | CLK_SET_RATE_ALTERNATE, + 0, "mout_cpu", "sclk_mpll"), MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), - MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), + MUX_FA(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, + CLK_SET_RATE_PARENT, 0, "mout_mpll", NULL), MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1), MUX(none, "sclk_bpll", mout_bpll_p, SRC_CDREX, 0, 1), MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP2, 0, 1),