From patchwork Mon Aug 12 10:02:13 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas C Sajjan X-Patchwork-Id: 2842951 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3E50FBF546 for ; Mon, 12 Aug 2013 10:02:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1BBFB2021B for ; Mon, 12 Aug 2013 10:02:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4F4DC2022D for ; Mon, 12 Aug 2013 10:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755963Ab3HLKCe (ORCPT ); Mon, 12 Aug 2013 06:02:34 -0400 Received: from mail-pd0-f182.google.com ([209.85.192.182]:53627 "EHLO mail-pd0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756027Ab3HLKCd (ORCPT ); Mon, 12 Aug 2013 06:02:33 -0400 Received: by mail-pd0-f182.google.com with SMTP id r10so3220060pdi.41 for ; Mon, 12 Aug 2013 03:02:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+BeUN+/HpHOUxaqdqfWWJASLR2pEi8q/ybNCbYocD+c=; b=AqZ/ggtNCigI1yWv2GKo2Dp2VlzlAQqIlvPOcYwuFcgDWwwDkQNdVbaWDthh4dx5lI mb9FpOna+Ng+Yo84GT4wg7Poy6N+/2mk5qdaTkbsM3pHxJGRtELF3OVvLo7QprS1lHPF OcKxPx6WjJo1nADtsbLw3x2AWB6szMSTk31NWwn6aCRRPosGQVObq2o8h52R0V2GJ61l BYtt+aIILxlG8cpQq5LG1fj0Ky3KTWwNqMQ1G5zoH2y48UXn9MbvU1qwzZB0iF7EU6rB gFyy6QL0xTtIynwyRPRbulkmtjqoBk+7Qzv5r/YpOn3FXRXyi2rZncAXj1jG959VTUu+ ZQ2g== X-Gm-Message-State: ALoCoQnqyU/WcOzZq1vMzk+rLu0VnhAKuIJeT+0fSDHNdfN2+Hk1UDD5Ke0WDusDMuAy/gvrMO7p X-Received: by 10.67.3.34 with SMTP id bt2mr7275382pad.3.1376301752637; Mon, 12 Aug 2013 03:02:32 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id ll5sm38951263pab.19.2013.08.12.03.02.27 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 12 Aug 2013 03:02:31 -0700 (PDT) From: Vikas Sajjan To: mturquette@linaro.org, linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, t.figa@samsung.com, dianders@chromium.org, patches@linaro.org, linaro-kernel@lists.linaro.org Subject: [PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC Date: Mon, 12 Aug 2013 15:32:13 +0530 Message-Id: <1376301734-21847-2-git-send-email-vikas.sajjan@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1376301734-21847-1-git-send-email-vikas.sajjan@linaro.org> References: <1376301734-21847-1-git-send-email-vikas.sajjan@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds GPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan --- drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index a9916a4..c400e82 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -494,6 +494,21 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), }; +static struct samsung_pll_rate_table gpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(1400000000, 175, 3, 0), /* for 466MHz */ + PLL_35XX_RATE(800000000, 100, 3, 0), /* for 400MHz, 200MHz */ + PLL_35XX_RATE(667000000, 389, 7, 1), /* for 333MHz, 222MHz, 166MHz */ + PLL_35XX_RATE(600000000, 200, 4, 1), /* for 300MHz, 200MHz, 150MHz */ + PLL_35XX_RATE(533000000, 533, 12, 1), /* for 533MHz, 266MHz, 133MHz */ + PLL_35XX_RATE(450000000, 450, 12, 1), /* for 450Hz */ + PLL_35XX_RATE(400000000, 100, 3, 1), + PLL_35XX_RATE(333000000, 222, 4, 2), + PLL_35XX_RATE(200000000, 100, 3, 2), + { }, +}; + static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ @@ -565,8 +580,10 @@ static void __init exynos5250_clk_init(struct device_node *np) fin_pll_rate = _get_rate("fin_pll"); - if (fin_pll_rate == 24 * MHZ) + if (fin_pll_rate == 24 * MHZ) { exynos5250_plls[epll].rate_table = epll_24mhz_tbl; + exynos5250_plls[gpll].rate_table = gpll_24mhz_tbl; + } vpllsrc = __clk_lookup("mout_vpllsrc"); if (vpllsrc)