From patchwork Thu Aug 15 03:27:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shirish S X-Patchwork-Id: 2844958 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BA6839F239 for ; Thu, 15 Aug 2013 03:04:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C55C8204B9 for ; Thu, 15 Aug 2013 03:04:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id AFA21204D3 for ; Thu, 15 Aug 2013 03:04:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760143Ab3HODEz (ORCPT ); Wed, 14 Aug 2013 23:04:55 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:12123 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759979Ab3HODEy (ORCPT ); Wed, 14 Aug 2013 23:04:54 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRJ00ERKXW3NFG0@mailout2.samsung.com>; Thu, 15 Aug 2013 12:04:52 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 79.D4.11618.4554C025; Thu, 15 Aug 2013 12:04:52 +0900 (KST) X-AuditID: cbfee691-b7fef6d000002d62-ce-520c45546804 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id DD.67.32250.4554C025; Thu, 15 Aug 2013 12:04:52 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MRJ006YNXVX1Q50@mmp1.samsung.com>; Thu, 15 Aug 2013 12:04:52 +0900 (KST) From: Shirish S To: inki.dae@samsung.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Cc: linux-samsung-soc@vger.kernel.org, airlied@linux.ie, kgene.kim@samsung.com, shirish@chromium.org Subject: [PATCH 2/3] ARM: dts: arndale: Add hdmi phy settings Date: Thu, 15 Aug 2013 08:57:04 +0530 Message-id: <1376537225-3815-3-git-send-email-s.shirish@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1376537225-3815-1-git-send-email-s.shirish@samsung.com> References: <1376537225-3815-1-git-send-email-s.shirish@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrOLMWRmVeSWpSXmKPExsWyRsSkSjfElSfIYNYURYvecyeZLOYfOcdq ceXrezaLSfcnsFj0LrjKZjHj/D4mi6YdB9kc2D1mN1xk8dj+7QGrx/3u40wefVtWMXp83iQX wBrFZZOSmpNZllqkb5fAlfHo8Hu2goXKFet2H2JrYHwg0cXIySEhYCIx9fpaJghbTOLCvfVs XYxcHEICSxkl+q6dYIUpunDqDQtEYhGjxKdz7awQzmwmiZ7J08Cq2ATUJS5OXs0MYosIhEv8 vzqFHcRmFkiT6Dy7kA3EFhawk1j/fibYOhYBVYn3TZcZQWxeAReJ+TN+QW1TlOh+NgGsnlPA VeLGts8sILYQUM3bLTeZQBZLCMxjl7h14Do7xCABiW+TDwEVcQAlZCU2HWCGmCMpcXDFDZYJ jMILGBlWMYqmFiQXFCelF5nqFSfmFpfmpesl5+duYgQG+ul/zybuYLx/wPoQYzLQuInMUqLJ +cBIySuJNzQ2M7IwNTE1NjK3NCNNWEmcV73FOlBIID2xJDU7NbUgtSi+qDQntfgQIxMHp1QD 4+ITtnVScT4rrXrW3So6lKvb77VU7DWjz9m0sPcK8jM4FY95dlq0nJsoLVT6+aL7MR7dXYWT s40+2DZvr3zygTdzV+AURYHpiwU5v+/4LPjhz/uJXD1zJSberDT6GWnf2rWXlYX7cWKDd9SU jPM7d+2xPsN/cypLu9aqD5NW8QfoX/YLsc+docRSnJFoqMVcVJwIAKMdxOKKAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrCIsWRmVeSWpSXmKPExsVy+t9jAd0QV54gg+MTJSx6z51ksph/5Byr xZWv79ksJt2fwGLRu+Aqm8WM8/uYLJp2HGRzYPeY3XCRxWP7twesHve7jzN59G1ZxejxeZNc AGtUA6NNRmpiSmqRQmpecn5KZl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtAd SgpliTmlQKGAxOJiJX07TBNCQ9x0LWAaI3R9Q4LgeowM0EDCGsaMR4ffsxUsVK5Yt/sQWwPj A4kuRk4OCQETiQun3rBA2GISF+6tZ+ti5OIQEljEKPHpXDsrhDObSaJn8jRWkCo2AXWJi5NX M4PYIgLhEv+vTmEHsZkF0iQ6zy5kA7GFBewk1r+fyQRiswioSrxvuswIYvMKuEjMn/GLFWKb okT3swlg9ZwCrhI3tn0Gu0IIqObtlptMExh5FzAyrGIUTS1ILihOSs811CtOzC0uzUvXS87P 3cQIjqNnUjsYVzZYHGIU4GBU4uHd0MEdJMSaWFZcmXuIUYKDWUmEN0abJ0iINyWxsiq1KD++ qDQntfgQYzLQVROZpUST84ExnlcSb2hsYm5qbGppYmFiZkmasJI474FW60AhgfTEktTs1NSC 1CKYLUwcnFINjNbTAs7z3ylzOeilEP3o65Na8Zrl74Oq9r3fc/nP+tlPtl/S/Du74Jf2olSH sCmfraL/tSxebNjWbKHWeSzJpoBbU832e8ov5ewZv6ME5R7299jcyJjm+mLX9qrnL/skODds NX/L2flT6usCjYobNQt+7D69vOrw9PYnbd4x3zLiHfLYM1ujvZVYijMSDbWYi4oTAV5zvFnn AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch moves the hdmi phy setting to arndale dts, as its more of a per board configuration and also shall be easier for supporting future chipsets. Signed-off-by: Shirish S --- arch/arm/boot/dts/exynos5250-arndale.dts | 120 ++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index abc7272..59db48a 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -424,6 +424,126 @@ hdmi { hpd-gpio = <&gpx3 7 2>; + hdmiphy-confs { + nr-confs = <13>; + conf0: conf0 { + clock-frequency = <25200000>; + conf = /bits/ 8 < + 0x01 0x51 0x2A 0x75 0x40 0x01 0x00 0x08 + 0x82 0x80 0xfc 0xd8 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xf4 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf1: conf1 { + clock-frequency = <27000000>; + conf = /bits/ 8 < + 0x01 0xd1 0x22 0x51 0x40 0x08 0xfc 0x20 + 0x98 0xa0 0xcb 0xd8 0x45 0xa0 0xac 0x80 + 0x06 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xe4 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf2: conf2 { + clock-frequency = <27027000>; + conf = /bits/ 8 < + 0x01 0xd1 0x2d 0x72 0x40 0x64 0x12 0x08 + 0x43 0xa0 0x0e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xe3 0x24 0x00 0x00 0x00 0x01 0x00 + >; + }; + conf3: conf3 { + clock-frequency = <36000000>; + conf = /bits/ 8 < + 0x01 0x51 0x2d 0x55 0x40 0x01 0x00 0x08 + 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xab 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf4: conf4 { + clock-frequency = <40000000>; + conf = /bits/ 8 < + 0x01 0x51 0x32 0x55 0x40 0x01 0x00 0x08 + 0x82 0x80 0x2c 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x9a 0x24 0x00 0x00 0x00 0x01 0x80 + >; + }; + conf5: conf5 { + clock-frequency = <65000000>; + conf = /bits/ 8 < + 0x01 0xd1 0x36 0x34 0x40 0x1e 0x0a 0x08 + 0x82 0xa0 0x45 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xbd 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf6: conf6 { + clock-frequency = <74176000>; + conf = /bits/ 8 < + 0x01 0xd1 0x3e 0x35 0x40 0x5b 0xde 0x08 + 0x82 0xa0 0x73 0xd9 0x45 0xa0 0xac 0x80 + 0x56 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xa6 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf7: conf7 { + clock-frequency = <74250000>; + conf = /bits/ 8 < + 0x01 0xd1 0x1f 0x10 0x40 0x40 0xf8 0x08 + 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80 + 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xa5 0x24 0x01 0x00 0x00 0x01 0x00 + >; + }; + conf8: conf8 { + clock-frequency = <83500000>; + conf = /bits/ 8 < + 0x01 0xd1 0x23 0x11 0x40 0x0c 0xfb 0x08 + 0x85 0xa0 0xd1 0xd8 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x93 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf9: conf9 { + clock-frequency = <106500000>; + conf = /bits/ 8 < + 0x01 0xd1 0x2c 0x12 0x40 0x0c 0x09 0x08 + 0x84 0xa0 0x0a 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x73 0x24 0x01 0x00 0x00 0x01 0x80 + >; + }; + conf10: conf10 { + clock-frequency = <108000000>; + conf = /bits/ 8 < + 0x01 0x51 0x2d 0x15 0x40 0x01 0x00 0x08 + 0x82 0x80 0x0e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0xc7 0x25 0x03 0x00 0x00 0x01 0x80 + >; + }; + conf11: conf11 { + clock-frequency = <146250000>; + conf = /bits/ 8 < + 0x01 0xd1 0x3d 0x15 0x40 0x18 0xfd 0x08 + 0x83 0xa0 0x6e 0xd9 0x45 0xa0 0xac 0x80 + 0x08 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x50 0x25 0x03 0x00 0x00 0x01 0x80 + >; + }; + conf12: conf12 { + clock-frequency = <148500000>; + conf = /bits/ 8 < + 0x01 0xd1 0x1f 0x00 0x40 0x40 0xf8 0x08 + 0x81 0xa0 0xba 0xd8 0x45 0xa0 0xac 0x80 + 0x3c 0x80 0x11 0x04 0x02 0x22 0x44 0x86 + 0x54 0x4b 0x25 0x03 0x00 0x00 0x01 0x00 + >; + }; + }; vdd_osc-supply = <&ldo10_reg>; vdd_pll-supply = <&ldo8_reg>; vdd-supply = <&ldo8_reg>;