From patchwork Wed Aug 21 06:43:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuvaraj CD X-Patchwork-Id: 2847519 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7F2DA9F239 for ; Wed, 21 Aug 2013 06:44:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 523D9201FB for ; Wed, 21 Aug 2013 06:44:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E784820172 for ; Wed, 21 Aug 2013 06:44:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752179Ab3HUGoI (ORCPT ); Wed, 21 Aug 2013 02:44:08 -0400 Received: from mail-pd0-f178.google.com ([209.85.192.178]:63371 "EHLO mail-pd0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752068Ab3HUGoH (ORCPT ); Wed, 21 Aug 2013 02:44:07 -0400 Received: by mail-pd0-f178.google.com with SMTP id w10so34499pde.23 for ; Tue, 20 Aug 2013 23:44:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=50anuR32mWC+C7YFUELFz8qjQMwZRGyqvTTdLJ7wBuk=; b=UV9byIrxonO43QCq7QNwNJl6YRcb+I5slL0KjLeoueHYo90gKC0Mht1BCZihnjblMq Yse2R3V65n2lVPow4dmvZ1VCFVrsotH0+HGfKnkplxELJS9OiOAcE0xzaPD2jVJNC3iH gEfUuZqn2ErPfpO0JbDktZfR2GKu5Lzg8suqOHs1ROL9N8LWvb9K1RKJYurQuBJBkmrl ccFl7cwxAvIQ1S5bXsd9SLevdIQXjYQXkSmxFpl6k7Pbo5/q1IyZF2+asF9cgd4MATFH 40ADvKhx+wV47/PRonoGSIQ2AZ9CcReX1TmuCbLKBgw+reRQA07WSla/a9Yhz0a/6NqL LYUQ== X-Received: by 10.66.248.130 with SMTP id ym2mr1177624pac.177.1377067447076; Tue, 20 Aug 2013 23:44:07 -0700 (PDT) Received: from yuvaraj-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id pq1sm6360451pbb.26.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 20 Aug 2013 23:44:06 -0700 (PDT) From: Yuvaraj Kumar C D To: linux-samsung-soc@vger.kernel.org, linux-mmc@vger.kernel.org, kgene.kim@samsung.com Cc: ks.giri@samsung.com, Yuvaraj Kumar C D Subject: [PATCH V2] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC Date: Wed, 21 Aug 2013 12:13:53 +0530 Message-Id: <1377067433-28373-1-git-send-email-yuvaraj.cd@samsung.com> X-Mailer: git-send-email 1.7.9.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the device tree node entries for exynos5420 SOC. Exynos5420 has a different version of DWMMC controller,so a new compatible string is used to distinguish it from the prior SOC's. changes since V1: 1.disable node by status = disabled in SOC file 2.enable node by status = okay in board specific file Signed-off-by: Yuvaraj Kumar C D --- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 ++ arch/arm/boot/dts/exynos5420-smdk5420.dts | 38 ++++++++++++++++++++ arch/arm/boot/dts/exynos5420.dtsi | 36 +++++++++++++++++++ 3 files changed, 76 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 6d1c098..84cd56f 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -16,6 +16,8 @@ Required Properties: specific extensions. - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. + - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 + specific extensions. * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..6e65278 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -31,6 +31,44 @@ }; }; + dwmmc0@12200000 { + status = "okay"; + num-slots = <1>; + broken-cd; + bypass-smu; + supports-highspeed; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + dwmmc2@12220000 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + fifo-depth = <0x80>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + dp-controller@145B0000 { pinctrl-names = "default"; pinctrl-0 = <&dp_hpd>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 5353e32..694e7f1 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -22,6 +22,9 @@ compatible = "samsung,exynos5420"; aliases { + mshc0 = &dwmmc_0; + mshc1 = &dwmmc_1; + mshc2 = &dwmmc_2; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -84,6 +87,39 @@ clock-names = "mfc"; }; + dwmmc_0: dwmmc0@12200000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x2000>; + clocks = <&clock 351>, <&clock 132>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + dwmmc_1: dwmmc1@12210000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x2000>; + clocks = <&clock 352>, <&clock 133>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + dwmmc_2: dwmmc2@12220000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x2000>; + clocks = <&clock 353>, <&clock 134>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>;