From patchwork Fri Aug 23 06:57:55 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2848544 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4A4EA9F239 for ; Fri, 23 Aug 2013 06:36:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 75F27201F3 for ; Fri, 23 Aug 2013 06:36:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7C78F201F2 for ; Fri, 23 Aug 2013 06:36:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754755Ab3HWGgN (ORCPT ); Fri, 23 Aug 2013 02:36:13 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:45448 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754702Ab3HWGgN (ORCPT ); Fri, 23 Aug 2013 02:36:13 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRZ00KEO1046R90@mailout1.samsung.com> for linux-samsung-soc@vger.kernel.org; Fri, 23 Aug 2013 15:36:12 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.122]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 6B.11.29948.CD207125; Fri, 23 Aug 2013 15:36:12 +0900 (KST) X-AuditID: cbfee691-b7f4a6d0000074fc-e0-521702dc2bfa Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 38.F3.05832.BD207125; Fri, 23 Aug 2013 15:36:12 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MRZ006GL0ZR9Y80@mmp2.samsung.com>; Fri, 23 Aug 2013 15:36:11 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, inki.dae@samsung.com, s.nawrocki@samsung.com, thomas.abraham@linaro.org, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH v2 2/5] clk/exynos5420: add gate clock for mixer sysmmu Date: Fri, 23 Aug 2013 12:27:55 +0530 Message-id: <1377241078-11808-3-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1377241078-11808-1-git-send-email-rahul.sharma@samsung.com> References: <1377241078-11808-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeLIzCtJLcpLzFFi42JZI2JSpXuHSTzIoHcLl8Wk+xNYLL7v+sJu 0bvgKpvFpsfXWC1mnN/HZPF0wkU2i4Uv4i2mLDrManH4TTurxbEZSxgduDx2zrrL7nHn2h42 j81L6j36tqxi9Pi8SS6ANYrLJiU1J7MstUjfLoEr4/XPC8wF3/kq9nVMY2tgPMXTxcjJISFg InFz6352CFtM4sK99WxdjFwcQgJLGSVWPJ3GAlM0990yJojEdEaJxRMb2SGc2UwSV1asBKti E9CVmH3wGSOILSLgLTH5zF+wImaBc4wSP/adYe1i5OAQFnCXOPbBAaSGRUBVYv6nl2D1vAIe EpdPtzFBbFOU6H42gQ3E5hTwlGiY94YVxBYCqrnfdxbsPAmBTewSs68sY4YYJCDxbfIhFpD5 EgKyEpsOMEPMkZQ4uOIGywRG4QWMDKsYRVMLkguKk9KLTPWKE3OLS/PS9ZLzczcxAmPg9L9n E3cw3j9gfYgxGWjcRGYp0eR8YAzllcQbGpsZWZiamBobmVuakSasJM6r3mIdKCSQnliSmp2a WpBaFF9UmpNafIiRiYNTqoFRpJpZMfufn0rYYh7LTyJ/fP9qTM7aonrKoL7a7UZvpXPPttsd k1h/M130ObVsmb3GJ4aJXk8exXF8jjGcUJ9y+WrtO/0PAvozPKtD7R/O7U5rVXY3uajRahT9 JvDTFO31p/Qe5pue/zV3t175/FPL/cQWlQn+K33jot+urKPyTCZlZ3fvDnUlluKMREMt5qLi RADXLcPplwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrIIsWRmVeSWpSXmKPExsVy+t9jQd07TOJBBt+vMlpMuj+BxeL7ri/s Fr0LrrJZbHp8jdVixvl9TBZPJ1xks1j4It5iyqLDrBaH37SzWhybsYTRgctj56y77B53ru1h 89i8pN6jb8sqRo/Pm+QCWKMaGG0yUhNTUosUUvOS81My89JtlbyD453jTc0MDHUNLS3MlRTy EnNTbZVcfAJ03TJzgI5SUihLzCkFCgUkFhcr6dthmhAa4qZrAdMYoesbEgTXY2SABhLWMGa8 /nmBueA7X8W+jmlsDYyneLoYOTkkBEwk5r5bxgRhi0lcuLeerYuRi0NIYDqjxOKJjewQzmwm iSsrVrKAVLEJ6ErMPviMEcQWEfCWmHzmL1gRs8A5Rokf+86wdjFycAgLuEsc++AAUsMioCox /9NLsHpeAQ+Jy6fboLYpSnQ/m8AGYnMKeEo0zHvDCmILAdXc7zvLNoGRdwEjwypG0dSC5ILi pPRcI73ixNzi0rx0veT83E2M4Ah7Jr2DcVWDxSFGAQ5GJR7eCc5iQUKsiWXFlbmHGCU4mJVE eA/8BQrxpiRWVqUW5ccXleakFh9iTAa6aiKzlGhyPjD680riDY1NzE2NTS1NLEzMLEkTVhLn PdhqHSgkkJ5YkpqdmlqQWgSzhYmDU6qBkXFi5bRvLutXThN8ZL/suLWTV9msiIzwbd5yN4q/ 6zzpmydwcqP7LfGpdzmKc55n/xB7PD3z+/GnBk5S337OKX66hsuqRydy0/zNjH+Zpir+lpmS c/IGN5PHulcyopXdzqVXjZNqHtRwGmXUlR8+1G/z0/K2r9YO2UtikS82lK9S9ij6t9bQU4ml OCPRUIu5qDgRAI3jCJT0AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding sysmmu clock for mixer for exynos5420. Signed-off-by: Rahul Sharma --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 1 + drivers/clk/samsung/clk-exynos5420.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 596a368..5758a69 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -180,6 +180,7 @@ clock which they consume. fimc_lite3 495 aclk_g3d 500 g3d 501 + smmu_mixer 502 Example 1: An example of a clock controller node is listed below. diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index a86cadc..4e0c13e 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -138,7 +138,7 @@ enum exynos5420_clks { aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0, gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0, aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0, - smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, + smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer, nr_clks, }; @@ -725,6 +725,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0), GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0), GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), + GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0), }; static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {