From patchwork Fri Aug 23 06:57:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2848547 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5B1BD9F239 for ; Fri, 23 Aug 2013 06:36:39 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8CECC201D5 for ; Fri, 23 Aug 2013 06:36:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6AE67201F3 for ; Fri, 23 Aug 2013 06:36:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754757Ab3HWGgS (ORCPT ); Fri, 23 Aug 2013 02:36:18 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:45459 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754754Ab3HWGgS (ORCPT ); Fri, 23 Aug 2013 02:36:18 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MRZ00J3L0ZANIA0@mailout1.samsung.com> for linux-samsung-soc@vger.kernel.org; Fri, 23 Aug 2013 15:36:17 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.125]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 35.DB.31253.1E207125; Fri, 23 Aug 2013 15:36:17 +0900 (KST) X-AuditID: cbfee690-b7f3b6d000007a15-3b-521702e1e9d3 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 60.97.09055.1E207125; Fri, 23 Aug 2013 15:36:17 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MRZ006GL0ZR9Y80@mmp2.samsung.com>; Fri, 23 Aug 2013 15:36:16 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, inki.dae@samsung.com, s.nawrocki@samsung.com, thomas.abraham@linaro.org, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH v2 5/5] clk/exynos5420: assign sclk_pixel id to pixel clock divider Date: Fri, 23 Aug 2013 12:27:58 +0530 Message-id: <1377241078-11808-6-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1377241078-11808-1-git-send-email-rahul.sharma@samsung.com> References: <1377241078-11808-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmphkeLIzCtJLcpLzFFi42JZI2JSq/uQSTzI4Ol/QYtJ9yewWHzf9YXd onfBVTaLTY+vsVrMOL+PyeLphItsFgtfxFtMWXSY1eLwm3ZWi2MzljA6cHnsnHWX3ePOtT1s HpuX1Hv0bVnF6PF5k1wAaxSXTUpqTmZZapG+XQJXxpkdtxkLunkr5u2LamCcwN3FyMkhIWAi cez1PXYIW0ziwr31bF2MXBxCAksZJS6cP8kIUzRz90ZmiMR0Rolf21YyQTizmSSuLXwGVsUm oCsx+yCELSLgLTH5zF92kCJmgXOMEj/2nWEFSQgLhEos2b6JCcRmEVCVWP/lD9huXgEPia8/ 70GtU5TofjaBDcTmFPCUaJj3BqxXCKjmft9ZsPskBNaxS/ybsZ8FYpCAxLfJh4BsDqCErMSm A8wQcyQlDq64wTKBUXgBI8MqRtHUguSC4qT0IhO94sTc4tK8dL3k/NxNjMAYOP3v2YQdjPcO WB9iTAYaN5FZSjQ5HxhDeSXxhsZmRhamJqbGRuaWZqQJK4nzqrdYBwoJpCeWpGanphakFsUX leakFh9iZOLglGpgLFgRtpq/223evMSdk7yV9t6IOFy4/261ejrn/8Nbi8+8aw9nYWetZJ3k XnyXIaRT9cnTq3VsWufO+B5bqdq+eNW7WKtvD6W/lrAIO+0yTRG+1LpkfUWHD7dvy6mwi6JV +iHv/OI3mLY+tlu4Z+l2meZcuZjOICmVtSIegrdbWKVnfjk/JyRMiaU4I9FQi7moOBEAUsKb Q5cCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrIIsWRmVeSWpSXmKPExsVy+t9jQd2HTOJBBpsXsltMuj+BxeL7ri/s Fr0LrrJZbHp8jdVixvl9TBZPJ1xks1j4It5iyqLDrBaH37SzWhybsYTRgctj56y77B53ru1h 89i8pN6jb8sqRo/Pm+QCWKMaGG0yUhNTUosUUvOS81My89JtlbyD453jTc0MDHUNLS3MlRTy EnNTbZVcfAJ03TJzgI5SUihLzCkFCgUkFhcr6dthmhAa4qZrAdMYoesbEgTXY2SABhLWMGac 2XGbsaCbt2LePqCDJnB3MXJySAiYSMzcvZEZwhaTuHBvPVsXIxeHkMB0Rolf21YyQTizmSSu LXzGCFLFJqArMfsghC0i4C0x+cxfdpAiZoFzjBI/9p1hBUkIC4RKLNm+iQnEZhFQlVj/5Q87 iM0r4CHx9ec9Roh1ihLdzyawgdicAp4SDfPegPUKAdXc7zvLNoGRdwEjwypG0dSC5ILipPRc Q73ixNzi0rx0veT83E2M4Ah7JrWDcWWDxSFGAQ5GJR7eCc5iQUKsiWXFlbmHGCU4mJVEeA/8 BQrxpiRWVqUW5ccXleakFh9iTAa6aiKzlGhyPjD680riDY1NzE2NTS1NLEzMLEkTVhLnPdBq HSgkkJ5YkpqdmlqQWgSzhYmDU6qBcd6RD5O5t7Ownlf+vTUpKvRR7hP7Q5Hxpjzf9SYz6S8/ 9n75ZgfjqyybuI/y39n4bK2pz8XIJ/c+nTM98yVPfX2NO9uCr9pV86+fivBmnBnFq7cquHqO 4cqJcx6aZu026F7uoy8n3r/VxS5lrcvkpXw7651KVVa68XnNmLHIX6BzMZPbh1WTdJVYijMS DbWYi4oTASYLq3z0AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP sclk_pixel is used to represent pixel clock divider on all exynos SoCs not as a gate clock. It is queried in driver to pass as the parent to hdmi clock while switching between parents. A new ID can be asssigned Pixel gate clock which is currently not in use. Pixel clock gate is default 'on'. Signed-off-by: Rahul Sharma --- drivers/clk/samsung/clk-exynos5420.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 5f9bc63..8eb3c42 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -463,7 +463,7 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4), DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8), DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4), - DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), + DIV(sclk_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4), /* Audio Block */ DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4), @@ -599,7 +599,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0), GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0), - GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel", + GATE(none, "sclk_pixel", "dout_hdmi_pixel", GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0), GATE(sclk_dp1, "sclk_dp1", "dout_dp1", GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),