From patchwork Wed Aug 28 12:03:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuvaraj CD X-Patchwork-Id: 2850705 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 042429F313 for ; Wed, 28 Aug 2013 12:03:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 87FF120444 for ; Wed, 28 Aug 2013 12:03:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B4F7E2035C for ; Wed, 28 Aug 2013 12:03:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755325Ab3H1MDX (ORCPT ); Wed, 28 Aug 2013 08:03:23 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:60635 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752979Ab3H1MDW (ORCPT ); Wed, 28 Aug 2013 08:03:22 -0400 Received: by mail-pa0-f48.google.com with SMTP id kp13so6143552pab.35 for ; Wed, 28 Aug 2013 05:03:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=arhv1hOrdGXUbS1WbGJ31dKKdkwXbCniv+xYhj7+ax4=; b=zCafbHIUZ060oP7PgpRYUG3DK3nNOSADR8hg6Ip4ivYOGqIyotYbeWo5dimKc10oLb Mevhpd2tKGsGzfLvKUl92XRD0uTOD4Z7my7Bs3JVvczDDPI+oz2Wv5MXyWlhHRO3NpyU r8uIic9D3/S+it7OXYwHteLjQtLVCh8bMJ/nbZePXhEp2nic9X7EbXY0o8+uUt9eeaOT JpajSkg+L0J6Kwvyluvd4f7W47IO/5QIe9LewiuSMH8/V5JyCGsG0Id3YnCaONcwSBZf fV5vmITq8pjSrjnynifz0Sav62DXtcs7vsCTnPJJbjevUuM0XRYGiBEOu9YVJTGIgPxA ugMA== X-Received: by 10.68.252.68 with SMTP id zq4mr27140980pbc.49.1377691401446; Wed, 28 Aug 2013 05:03:21 -0700 (PDT) Received: from yuvaraj-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id bg3sm30863844pbb.44.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 28 Aug 2013 05:03:20 -0700 (PDT) From: Yuvaraj Kumar C D To: linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com, devicetree@vger.kernel.org Cc: rob.herring@calxeda.com, pawel.moll@arm.com, mark.rutland@arm.com, swarren@wwwdotorg.org, ian.campbell@citrix.com, t.figa@samsung.com, dianders@chromium.org, cjb@laptop.org, thomas.abraham@linaro.org, ks.giri@samsung.com, Yuvaraj Kumar C D Subject: [PATCH V5] ARM: dts: Add dwmmc DT nodes for exynos5420 SOC Date: Wed, 28 Aug 2013 17:33:06 +0530 Message-Id: <1377691386-7085-1-git-send-email-yuvaraj.cd@samsung.com> X-Mailer: git-send-email 1.7.9.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the device tree node entries for exynos5420 SOC. Exynos5420 has a different version of DWMMC controller,so a new compatible string is used to distinguish it from the prior SOC's. This patch depends on mmc: dw_mmc: exynos: Add a new compatible string for exynos5420 changes since v4: 1.Droppped the bypass-smu binding property. 2.Used compatible string "samsung,exynos5250-dw-mshc" for controller instance which does not have SMU. changes since V3: 1.change fifo-depth size from 0x80 to 0x40 2.Move the below properties a.card-detect-delay b.samsung,dw-mshc-ciu-div c.samsung,dw-mshc-sdr-timing d.samsung,dw-mshc-ddr-timing from SOC dts to board dts file as suggested by Doug Anderson changes since V2: 1.dropped num-slots property from node as its not required if number of card slots available is 1. 2.Move the below properties a.fifo-depth b.card-detect-delay c.samsung,dw-mshc-ciu-div d.samsung,dw-mshc-sdr-timing e.samsung,dw-mshc-ddr-timing from board dts to SOC dts,as these are not board specific properties. 3.Updated the binding document exynos-dw-mshc.txt. changes since V1: 1.disable node by status = disabled in SOC file 2.enable node by status = okay in board specific file Signed-off-by: Yuvaraj Kumar C D --- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 2 + arch/arm/boot/dts/exynos5420-smdk5420.dts | 33 +++++++++++++++++ arch/arm/boot/dts/exynos5420.dtsi | 39 ++++++++++++++++++++ 3 files changed, 74 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 6d1c098..84cd56f 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -16,6 +16,8 @@ Required Properties: specific extensions. - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250 specific extensions. + - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 + specific extensions. * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index bafba25..3ce5c97 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -31,6 +31,39 @@ }; }; + dwmmc0@12200000 { + status = "okay"; + broken-cd; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; + }; + + dwmmc2@12220000 { + status = "okay"; + supports-highspeed; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + dp-controller@145B0000 { pinctrl-names = "default"; pinctrl-0 = <&dp_hpd>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index d537cd7..ccfa235 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -22,6 +22,9 @@ compatible = "samsung,exynos5420"; aliases { + mshc0 = &dwmmc_0; + mshc1 = &dwmmc_1; + mshc2 = &dwmmc_2; pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; @@ -84,6 +87,42 @@ clock-names = "mfc"; }; + dwmmc_0: dwmmc0@12200000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 75 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12200000 0x2000>; + clocks = <&clock 351>, <&clock 132>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + dwmmc_1: dwmmc1@12210000 { + compatible = "samsung,exynos5420-dw-mshc"; + interrupts = <0 76 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12210000 0x2000>; + clocks = <&clock 352>, <&clock 133>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + dwmmc_2: dwmmc2@12220000 { + compatible = "samsung,exynos5250-dw-mshc"; + interrupts = <0 77 0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x12220000 0x2000>; + clocks = <&clock 353>, <&clock 134>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>;