From patchwork Wed Aug 28 13:39:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikas C Sajjan X-Patchwork-Id: 2850782 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CBC9E9F313 for ; Wed, 28 Aug 2013 13:40:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A864E2042A for ; Wed, 28 Aug 2013 13:40:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 81A2F20413 for ; Wed, 28 Aug 2013 13:40:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752956Ab3H1NkS (ORCPT ); Wed, 28 Aug 2013 09:40:18 -0400 Received: from mail-pb0-f41.google.com ([209.85.160.41]:50357 "EHLO mail-pb0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752961Ab3H1NkO (ORCPT ); Wed, 28 Aug 2013 09:40:14 -0400 Received: by mail-pb0-f41.google.com with SMTP id rp2so6308856pbb.0 for ; Wed, 28 Aug 2013 06:40:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GmkxHYXss9lX/AyVMgipH7Pk1FG+NrGf40PwJitSJwQ=; b=nkZ+iUW1HIAAXnXIkmOBE2+Zr39xO0IJLbZ1NGby/2ZB00iaCw+v6ck3JhIjI0BNfj hYFoxovU5e2QqM1ss3l36FFnV1LJAqUwCZfzTWNrVl84ce9TTtia4oI/fByWQluDhozc 1r8DDqc7Aryy+g3eH1chug08sClZxQIWVyhPEHgt5ePAedieE9h4ZSMtMPr5w3shg6s8 HvmDVvBWDwAB7fYb2z0acszENYoHQvbqaxwGzVrcljg1K2EinlhcyOn9UGV5QmLoknMd T85tudoNawCU+b7o8pfEKtlMvaD8r4RbVWFeX7RShp214hWpBPVmDExLwPWsNif5wGOG 4JPQ== X-Gm-Message-State: ALoCoQkCuBlYi1sw1rVjxXNr81mG4cpimo74uBRkIa9JajBsR3z+0ZkRqTzun9thLLY7MFhweGCF X-Received: by 10.66.161.38 with SMTP id xp6mr15181601pab.145.1377697214402; Wed, 28 Aug 2013 06:40:14 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id fk4sm33976049pab.23.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 28 Aug 2013 06:40:13 -0700 (PDT) From: Vikas Sajjan To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, t.figa@samsung.com, mturquette@linaro.org, patches@linaro.org, linaro-kernel@lists.linaro.org, joshi@samsung.com Subject: [PATCH v2 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC Date: Wed, 28 Aug 2013 19:09:57 +0530 Message-Id: <1377697198-19097-2-git-send-email-vikas.sajjan@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1377697198-19097-1-git-send-email-vikas.sajjan@linaro.org> References: <1377697198-19097-1-git-send-email-vikas.sajjan@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adds GPLL freq table for exynos5250 SoC. Signed-off-by: Vikas Sajjan --- drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 00a80e4..6b7ad2a 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -494,6 +494,21 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), }; +static struct samsung_pll_rate_table gpll_24mhz_tbl[] __initdata = { + /* sorted in descending order */ + /* PLL_35XX_RATE(rate, m, p, s) */ + PLL_35XX_RATE(1400000000, 175, 3, 0), /* for 466MHz */ + PLL_35XX_RATE(800000000, 100, 3, 0), /* for 400MHz, 200MHz */ + PLL_35XX_RATE(666857142, 389, 7, 1), /* for 333MHz, 222MHz, 166MHz */ + PLL_35XX_RATE(600000000, 200, 4, 1), /* for 300MHz, 200MHz, 150MHz */ + PLL_35XX_RATE(533000000, 533, 12, 1), /* for 533MHz, 266MHz, 133MHz */ + PLL_35XX_RATE(450000000, 450, 12, 1), /* for 450Hz */ + PLL_35XX_RATE(400000000, 100, 3, 1), + PLL_35XX_RATE(333000000, 222, 4, 2), + PLL_35XX_RATE(200000000, 100, 3, 2), + { }, +}; + static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { /* sorted in descending order */ /* PLL_36XX_RATE(rate, m, p, s, k) */ @@ -561,8 +576,10 @@ static void __init exynos5250_clk_init(struct device_node *np) samsung_clk_register_mux(exynos5250_pll_pmux_clks, ARRAY_SIZE(exynos5250_pll_pmux_clks)); - if (_get_rate("fin_pll") == 24 * MHZ) + if (_get_rate("fin_pll") == 24 * MHZ) { exynos5250_plls[epll].rate_table = epll_24mhz_tbl; + exynos5250_plls[gpll].rate_table = gpll_24mhz_tbl; + } if (_get_rate("mout_vpllsrc") == 24 * MHZ) exynos5250_plls[vpll].rate_table = vpll_24mhz_tbl;