From patchwork Thu Aug 29 05:37:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 2851131 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 963B4BF546 for ; Thu, 29 Aug 2013 05:15:47 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C2C8C2024A for ; Thu, 29 Aug 2013 05:15:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CC4A420237 for ; Thu, 29 Aug 2013 05:15:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753518Ab3H2FPp (ORCPT ); Thu, 29 Aug 2013 01:15:45 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:52168 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752337Ab3H2FPo (ORCPT ); Thu, 29 Aug 2013 01:15:44 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MSA007LH199PC70@mailout3.samsung.com> for linux-samsung-soc@vger.kernel.org; Thu, 29 Aug 2013 14:15:34 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 2D.C2.22755.6F8DE125; Thu, 29 Aug 2013 14:15:34 +0900 (KST) X-AuditID: cbfee68f-b7f656d0000058e3-5f-521ed8f6970b Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 20.49.09055.5F8DE125; Thu, 29 Aug 2013 14:15:34 +0900 (KST) Received: from chromeserver-PowerEdge-T410.sisodomain.com ([107.108.73.106]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MSA00BFW19BFDJ0@mmp1.samsung.com>; Thu, 29 Aug 2013 14:15:33 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, inki.dae@samsung.com, s.nawrocki@samsung.com, thomas.abraham@linaro.org, tomasz.figa@gmail.com, joshi@samsung.com, r.sh.open@gmail.com, Rahul Sharma Subject: [PATCH v4 2/5] clk/exynos5420: add gate clock for mixer sysmmu Date: Thu, 29 Aug 2013 11:07:06 +0530 Message-id: <1377754629-31465-3-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1377754629-31465-1-git-send-email-rahul.sharma@samsung.com> References: <1377754629-31465-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupgkeLIzCtJLcpLzFFi42JZI2JSo/vthlyQwfHVPBaT7k9gsfi+6wu7 Re+Cq2wWmx5fY7WYcX4fk8XTCRfZLBa+iLeYsugwq8XhN+2sFsdmLGG0WLXrD6MDt8fOWXfZ Pe5c28PmsXlJvUffllWMHp83yQWwRnHZpKTmZJalFunbJXBlvP55gbngO1/Fvo5pbA2Mp3i6 GDk5JARMJH5cbGKGsMUkLtxbz9bFyMUhJLCUUWLdht3MMEWXNr5nhEgsYpTYc+UtE4Qzm0ni 4rflLCBVbAK6ErMPPmMEsUUEvCUmn/nLDlLELPCUUeLOin6guRwcwgLuEsfu+ILUsAioSsw/ tYANxOYV8JA4umslI8Q2RYnuZxPAyjkFPCU2rQ0DCQsBlez43cQCMlJCYBe7xLEVX9gh5ghI fJt8iAWkXkJAVmLTAaijJSUOrrjBMoFReAEjwypG0dSC5ILipPQiY73ixNzi0rx0veT83E2M wFg4/e9Z/w7GuwesDzEmA42byCwlmpwPjKW8knhDYzMjC1MTU2Mjc0sz0oSVxHnVWqwDhQTS E0tSs1NTC1KL4otKc1KLDzEycXBKNTCmrM4xvT+1veJAmaV4qui15IQLmw8vs7VzZ1vdZ2wj LOPEIrrwb8YCY5kFl85aTtd+lVf/8rG7QN3J4nf9Iu0XTM09FQSXcXTILT/x4t+ZxaZsmi77 j2+4Ym3KM5m/5WVI9LM8i4WmR+fU3BN9abP+gOc9du917z5cnBA2SXS97rRNEufbHl5SYinO SDTUYi4qTgQA7klkBZsCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKIsWRmVeSWpSXmKPExsVy+t9jAd1vN+SCDI5+ZbaYdH8Ci8X3XV/Y LXoXXGWz2PT4GqvFjPP7mCyeTrjIZrHwRbzFlEWHWS0Ov2lntTg2YwmjxapdfxgduD12zrrL 7nHn2h42j81L6j36tqxi9Pi8SS6ANaqB0SYjNTEltUghNS85PyUzL91WyTs43jne1MzAUNfQ 0sJcSSEvMTfVVsnFJ0DXLTMH6DIlhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZo IGENY8brnxeYC77zVezrmMbWwHiKp4uRk0NCwETi0sb3jBC2mMSFe+vZuhi5OIQEFjFK7Lny lgnCmc0kcfHbchaQKjYBXYnZB5+BdYgIeEtMPvOXHaSIWeApo8SdFf1A7RwcwgLuEsfu+ILU sAioSsw/tYANxOYV8JA4umsl1DZFie5nE8DKOQU8JTatDQMJCwGV7PjdxDKBkXcBI8MqRtHU guSC4qT0XEO94sTc4tK8dL3k/NxNjOBIeya1g3Flg8UhRgEORiUe3ojfskFCrIllxZW5hxgl OJiVRHhP7ZMLEuJNSaysSi3Kjy8qzUktPsSYDHTURGYp0eR8YBLIK4k3NDYxNzU2tTSxMDGz JE1YSZz3QKt1oJBAemJJanZqakFqEcwWJg5OqQbGE3YvoxuKVmqnMC49cuBHwt7VM3WFrS8K JEZYP1oTeOtMbpx3fv6izENZ1WzHd88wMuVcnP66j8lrc4TB4/RzzMtO/WQWck4VmOq99wR/ z5VUYS6RnPA5h4J9c+9dj/dzFlCYo/JAM/gOj/jkP1FKp5kTr64/UMe66uC8azwr+b69fxqW qzhRiaU4I9FQi7moOBEAWUwzBvgCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Adding sysmmu clock for mixer for exynos5420. Signed-off-by: Rahul Sharma --- Documentation/devicetree/bindings/clock/exynos5420-clock.txt | 1 + drivers/clk/samsung/clk-exynos5420.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt index 596a368..5758a69 100644 --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt @@ -180,6 +180,7 @@ clock which they consume. fimc_lite3 495 aclk_g3d 500 g3d 501 + smmu_mixer 502 Example 1: An example of a clock controller node is listed below. diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index a86cadc..4e0c13e 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -138,7 +138,7 @@ enum exynos5420_clks { aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0, gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0, aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0, - smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, + smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_mixer, nr_clks, }; @@ -725,6 +725,7 @@ static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0), GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0), GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0), + GATE(smmu_mixer, "smmu_mixer", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0), }; static struct samsung_pll_clock exynos5420_plls[nr_plls] __initdata = {