From patchwork Thu Aug 29 11:53:57 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuvaraj CD X-Patchwork-Id: 2851275 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 442259F2F4 for ; Thu, 29 Aug 2013 11:54:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2E33B201FF for ; Thu, 29 Aug 2013 11:54:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E8C44201FD for ; Thu, 29 Aug 2013 11:54:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754751Ab3H2LyN (ORCPT ); Thu, 29 Aug 2013 07:54:13 -0400 Received: from mail-pa0-f41.google.com ([209.85.220.41]:55343 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752608Ab3H2LyM (ORCPT ); Thu, 29 Aug 2013 07:54:12 -0400 Received: by mail-pa0-f41.google.com with SMTP id bj1so829670pad.28 for ; Thu, 29 Aug 2013 04:54:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=Jk/s/y4DyRz2H/GxEb7flibrrBDeW4Y6ib5UiN50Asg=; b=D2/8PYgT3HPJfsB8hRTC8KW4EIWmUML0HUxZs0D0Qqbc/LgGO9HmkKBMrjP8MWSeWa JEfonhBbDbCClhp6eCK3ppuFrCCibYgCFVEGNlXTImOd5pruq3SjMfuOmX30WnHILdwm BVhP/yOknSvmXP2kQT4UclGCxyr0q2F0NWquF8IRbFnIr5kqmwM7ZbNzIKodqhq5p8k4 fLMfCX6DpY3L4wKT9oUUU0/IJZeKi1NUt6aWaAyIcZHaGNOCRrEJSEaaIG4xUxZC6bAa Z07PZCywf+f3K556l9x+RvGX60pdt6ZCmjv6hwv74Q0q82EGwZg5PGg81hcsmVQZKPkh d6uQ== X-Received: by 10.68.190.197 with SMTP id gs5mr3189841pbc.90.1377777251922; Thu, 29 Aug 2013 04:54:11 -0700 (PDT) Received: from yuvaraj-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id om2sm37545671pbc.30.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 29 Aug 2013 04:54:10 -0700 (PDT) From: Yuvaraj Kumar C D To: linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com, devicetree@vger.kernel.org Cc: rob.herring@calxeda.com, pawel.moll@arm.com, mark.rutland@arm.com, swarren@wwwdotorg.org, ian.campbell@citrix.com, t.figa@samsung.com, dianders@chromium.org, cjb@laptop.org, thomas.abraham@linaro.org, ks.giri@samsung.com, Yuvaraj Kumar C D Subject: [PATCH] ARM: dts: update binding document exynos-dw-mshc.txt Date: Thu, 29 Aug 2013 17:23:57 +0530 Message-Id: <1377777238-25087-1-git-send-email-yuvaraj.cd@samsung.com> X-Mailer: git-send-email 1.7.9.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch updates the exynos-dw-mshc.txt.Currently we are using "pinctrl" binding property to describe the CMD and DATA line's of Mobile Storage Host Controller(mshc) node. Signed-off-by: Yuvaraj Kumar C D Reviewed-by: Doug Anderson --- .../devicetree/bindings/mmc/exynos-dw-mshc.txt | 34 ++++++++++---------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt index 84cd56f..646a902 100644 --- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt @@ -7,9 +7,9 @@ differences between the core Synopsis dw mshc controller properties described by synopsis-dw-mshc.txt and the properties used by the Samsung Exynos specific extensions to the Synopsis Designware Mobile Storage Host Controller. -Required Properties: +Required SoC Specific Properties: -* compatible: should be +* compatible: should be one of the following - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210 specific extensions. - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412 @@ -19,6 +19,8 @@ Required Properties: - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420 specific extensions. +Required Board Specific Properties: + * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface unit (ciu) clock. This property is applicable only for Exynos5 SoC's and ignored for Exynos4 SoC's. The valid range of divider value is 0 to 7. @@ -46,44 +48,42 @@ Required Properties: - if CIU clock divider value is 0 (that is divide by 1), both tx and rx phase shift clocks should be 0. -Required properties for a slot: - -* gpios: specifies a list of gpios used for command, clock and data bus. The - first gpio is the command line and the second gpio is the clock line. The - rest of the gpios (depending on the bus-width property) are the data lines in - no particular order. The format of the gpio specifier depends on the gpio - controller. +* pinctrl-0: Should specify pin control groups used for this controller. +* pinctrl-names: Should contain only one value - "default". +Required properties for a slot: + Refer synopsis-dw-mshc.txt Example: The MSHC controller node can be split into two portions, SoC specific and board specific portions as listed below. - dwmmc0@12200000 { + mshc@12200000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; interrupts = <0 75 0>; #address-cells = <1>; #size-cells = <0>; + clocks = <&clock 351>, <&clock 132>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + status = "disabled"; }; - dwmmc0@12200000 { + mshc@12200000 { + status = "okay"; num-slots = <1>; supports-highspeed; broken-cd; - fifo-depth = <0x80>; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; slot@0 { reg = <0>; bus-width = <8>; - gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>, - <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>, - <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>, - <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>, - <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>; }; };