From patchwork Fri Aug 30 09:47:43 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuvaraj CD X-Patchwork-Id: 2851848 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4F7DA9F2F4 for ; Fri, 30 Aug 2013 09:48:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 23C2020253 for ; Fri, 30 Aug 2013 09:48:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4F87D202E6 for ; Fri, 30 Aug 2013 09:48:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754792Ab3H3JsP (ORCPT ); Fri, 30 Aug 2013 05:48:15 -0400 Received: from mail-pd0-f181.google.com ([209.85.192.181]:54119 "EHLO mail-pd0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754717Ab3H3JsO (ORCPT ); Fri, 30 Aug 2013 05:48:14 -0400 Received: by mail-pd0-f181.google.com with SMTP id g10so1631593pdj.40 for ; Fri, 30 Aug 2013 02:48:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Mt7VdMWidc70Lx1+9o5tU0d5nUfNfUlvGTzYpAWO3tY=; b=Yda5SsK2KjbszZjWxutAwwnXOoZWB6/Z/DW3P1iiZbhslOh3s+lZoJ0M3qEF/2heU7 M554yfIi7KCCommegpdgbY02Wn25m2g4OjqixH1/4BGKtBqCb6baYQKxL6xODeHI7Qyg e2QpiLJhzfhAmgiPr7uojt4aA5VDExcCnkPfxkrH4fEPASkTuKHuR5B3/GrqTElKYuKt GUTVw/oq8jgzRz5zrdMYV15OaBKCuZ6W0JGnWUYeKaxAD9oBok10OoMLWvySQYyd8z3M 81+28ZwkHdAAdBU9St9i37QxH7xGshJFazE8nJKhk4Uf7V8pjMwSpz8CIx1xX2eMHxuW e7SQ== X-Received: by 10.68.76.101 with SMTP id j5mr8956091pbw.67.1377856094114; Fri, 30 Aug 2013 02:48:14 -0700 (PDT) Received: from yuvaraj-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id lm2sm46712834pab.2.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 30 Aug 2013 02:48:13 -0700 (PDT) From: Yuvaraj Kumar C D To: linux-mmc@vger.kernel.org, linux-samsung-soc@vger.kernel.org, cjb@laptop.org, jh80.chung@samsung.com, tgih.jun@samsung.com Cc: ks.giri@samsung.com, t.figa@samsung.com, alim.akhtar@samsung.com, dianders@chromium.org, Yuvaraj Kumar C D Subject: [RFC V4 4/4] mmc: dw_mmc: exynos: configure SMU in exynos5420. Date: Fri, 30 Aug 2013 15:17:43 +0530 Message-Id: <1377856063-3391-5-git-send-email-yuvaraj.cd@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1377856063-3391-1-git-send-email-yuvaraj.cd@samsung.com> References: <1377856063-3391-1-git-send-email-yuvaraj.cd@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.9 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos5420 Mobile Storage Host controller has Security Management Unit (SMU) for channel 0 and channel 1 (mainly for eMMC).This patch configures SMU for exynos5420. This patch is on top of the below patches [1]mmc: dw_mmc: Add exynos resume_noirq callback to clear WAKEUP_INT. [2]ARM: dts: Add dwmmc DT nodes for exynos5420 SOC. changes since V3: 1.Added new compatible string "samsung,exynos5420-dw-mshc-smu" for the host with SMU. 2.Used compatible string "samsung,exynos5420-dw-mshc-smu" for controller instance which has SMU. 3.Used compatible string "samsung,exynos5420-dw-mshc" for controller instance which does not have SMU. changes since V2: 1.Droppped the bypass-smu quirk. 2.Changed the subject line for this patch add a quirk for SMU -> configure SMU in exynos5420 changes since V1: 1.avoid code duplication by calling dw_mci_exynos_priv_init in resume path. Signed-off-by: Yuvaraj Kumar C D Signed-off-by: Alim Akhtar --- drivers/mmc/host/dw_mmc-exynos.c | 38 +++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 19c845b..2f6ac82 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -35,12 +35,32 @@ #define EXYNOS4210_FIXED_CIU_CLK_DIV 2 #define EXYNOS4412_FIXED_CIU_CLK_DIV 4 +/* Block number in eMMC */ +#define DWMCI_BLOCK_NUM 0xFFFFFFFF + +#define SDMMC_EMMCP_BASE 0x1000 +#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010) +#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200) +#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204) +#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C) + +/* SMU control bits */ +#define DWMCI_MPSCTRL_SECURE_READ_BIT BIT(7) +#define DWMCI_MPSCTRL_SECURE_WRITE_BIT BIT(6) +#define DWMCI_MPSCTRL_NON_SECURE_READ_BIT BIT(5) +#define DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4) +#define DWMCI_MPSCTRL_USE_FUSE_KEY BIT(3) +#define DWMCI_MPSCTRL_ECB_MODE BIT(2) +#define DWMCI_MPSCTRL_ENCRYPTION BIT(1) +#define DWMCI_MPSCTRL_VALID BIT(0) + /* Variations in Exynos specific dw-mshc controller */ enum dw_mci_exynos_type { DW_MCI_TYPE_EXYNOS4210, DW_MCI_TYPE_EXYNOS4412, DW_MCI_TYPE_EXYNOS5250, DW_MCI_TYPE_EXYNOS5420, + DW_MCI_TYPE_EXYNOS5420_SMU, }; /* Exynos implementation specific driver private data */ @@ -67,6 +87,9 @@ static struct dw_mci_exynos_compatible { }, { .compatible = "samsung,exynos5420-dw-mshc", .ctrl_type = DW_MCI_TYPE_EXYNOS5420, + }, { + .compatible = "samsung,exynos5420-dw-mshc-smu", + .ctrl_type = DW_MCI_TYPE_EXYNOS5420_SMU, }, }; @@ -74,6 +97,15 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv = host->priv; + if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) { + mci_writel(host, MPSBEGIN0, 0); + mci_writel(host, MPSEND0, DWMCI_BLOCK_NUM); + mci_writel(host, MPSCTRL0, DWMCI_MPSCTRL_SECURE_WRITE_BIT | + DWMCI_MPSCTRL_NON_SECURE_READ_BIT | + DWMCI_MPSCTRL_VALID | + DWMCI_MPSCTRL_NON_SECURE_WRITE_BIT); + } + return 0; } @@ -82,7 +114,8 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host) struct dw_mci_exynos_priv_data *priv = host->priv; if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5250 || - priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420) + priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420 || + priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU) host->bus_hz /= (priv->ciu_div + 1); else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412) host->bus_hz /= EXYNOS4412_FIXED_CIU_CLK_DIV; @@ -107,6 +140,7 @@ static int dw_mci_exynos_resume(struct device *dev) { struct dw_mci *host = dev_get_drvdata(dev); + dw_mci_exynos_priv_init(host); return dw_mci_resume(host); } @@ -226,6 +260,8 @@ static const struct of_device_id dw_mci_exynos_match[] = { .data = &exynos_drv_data, }, { .compatible = "samsung,exynos5420-dw-mshc", .data = &exynos_drv_data, }, + { .compatible = "samsung,exynos5420-dw-mshc-smu", + .data = &exynos_drv_data, }, {}, }; MODULE_DEVICE_TABLE(of, dw_mci_exynos_match);