From patchwork Tue Sep 3 11:34:31 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 2853191 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7060E9F494 for ; Tue, 3 Sep 2013 11:35:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BB12720378 for ; Tue, 3 Sep 2013 11:35:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 92C5A20351 for ; Tue, 3 Sep 2013 11:35:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932770Ab3ICLe4 (ORCPT ); Tue, 3 Sep 2013 07:34:56 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:41313 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932595Ab3ICLe4 (ORCPT ); Tue, 3 Sep 2013 07:34:56 -0400 Received: by mail-pa0-f48.google.com with SMTP id kp13so6247125pab.7 for ; Tue, 03 Sep 2013 04:34:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V0EysRTzA6h9wQbXoyHyGTzhr+t/wZTQKvbpWqz15vU=; b=mzCXnOpRbTgrcVdVzwxkjYctP7uarr+kSgneXVaYbvpBHyMV7zvratQ34fznVYANNy UJPcCiWo+ccdWjNN+Qf6hrtjrT4BoIse2l7dyxgY8FZBEFoKEPVxJryEtG9vRgNXAQhU Rok9IR/tCaKklvIVQrFcXfajCqJGYyHtc07tI4Pko8CTSYQbpzUkd7Pqceu7ByVV0HZb 6HuiQOMhTr/TcQrBiCMH0wkcKtGv/CWll2Xu0ysSmiLuT9+YW3V5isX0hH9USFiFxB42 1XuG/sKt02acVFXJTIA4bb1CR8cKd7pG2O9J8f+80eQDjkllueV0oJCpPRsvANa0+vMK QbwA== X-Gm-Message-State: ALoCoQmIIPksvod4iQbCWK5+onBk00Dc/nvNUW7hyeHGoxTB6s8EROL/mkpfKD5G3fNjShr9K+wv X-Received: by 10.68.180.35 with SMTP id dl3mr1334723pbc.197.1378208095984; Tue, 03 Sep 2013 04:34:55 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id ts6sm21918962pbc.12.1969.12.31.16.00.00 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 03 Sep 2013 04:34:55 -0700 (PDT) From: Chander Kashyap To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, mturquette@linaro.org, thomas.abraham@linaro.org, Chander Kashyap Subject: [RFC Patch v2 3/3] clk: samsung: Exynos5250: Add alternate parent name for mout_cpu Date: Tue, 3 Sep 2013 17:04:31 +0530 Message-Id: <1378208072-10173-4-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1378208072-10173-1-git-send-email-chander.kashyap@linaro.org> References: <1378208072-10173-1-git-send-email-chander.kashyap@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Temporary parent migration is required during cpu frequency scaling. Hence this patch adds support to supply alternate parent name for cpu clock i.e. "mout_cpu". Signed-off-by: Chander Kashyap --- drivers/clk/samsung/clk-exynos5250.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index d90e593..aec2e09 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -239,7 +239,9 @@ static struct samsung_mux_clock exynos5250_pll_pmux_clks[] __initdata = { static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { MUX_A(none, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, "mout_apll"), - MUX_A(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"), + MUX_FA(none, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, + CLK_SET_RATE_PARENT | CLK_SET_RATE_TEMP_PARENT, + 0, "mout_cpu", "sclk_mpll"), MUX(none, "mout_mpll_fout", mout_mpll_fout_p, PLL_DIV2_SEL, 4, 1), MUX_A(none, "sclk_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"), MUX(none, "mout_bpll_fout", mout_bpll_fout_p, PLL_DIV2_SEL, 0, 1),