From patchwork Fri Sep 6 10:12:41 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 2854480 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2BF7EC0AB5 for ; Fri, 6 Sep 2013 10:14:52 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D4B9A202AE for ; Fri, 6 Sep 2013 10:14:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 66AA9202B1 for ; Fri, 6 Sep 2013 10:14:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751272Ab3IFKOb (ORCPT ); Fri, 6 Sep 2013 06:14:31 -0400 Received: from mailout2.w1.samsung.com ([210.118.77.12]:25636 "EHLO mailout2.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750966Ab3IFKO1 (ORCPT ); Fri, 6 Sep 2013 06:14:27 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MSP00LCV8F85X50@mailout2.w1.samsung.com>; Fri, 06 Sep 2013 11:14:19 +0100 (BST) X-AuditID: cbfec7f4-b7f0a6d000007b1b-f5-5229aafbfbb6 Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id B5.74.31515.BFAA9225; Fri, 06 Sep 2013 11:14:19 +0100 (BST) Received: from AMDC1061.digital.local ([106.116.147.88]) by eusync3.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MSP00I458FJKX90@eusync3.samsung.com>; Fri, 06 Sep 2013 11:14:19 +0100 (BST) From: Andrzej Hajda To: linux-arm-kernel@lists.infradead.org Cc: Andrzej Hajda , Kukjin Kim , Mike Turquette , Kyungmin Park , devicetree@vger.kernel.org (moderated list:OPEN FIRMWARE AND...), linux-samsung-soc@vger.kernel.org (moderated list:ARM/S5P EXYNOS AR...) Subject: [PATCH v2 12/12] clk: exynos5440: replace clock ID private enums with IDs from DT header Date: Fri, 06 Sep 2013 12:12:41 +0200 Message-id: <1378462361-13680-13-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.8.1.2 In-reply-to: <1378462361-13680-1-git-send-email-a.hajda@samsung.com> References: <1378462361-13680-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrIJMWRmVeSWpSXmKPExsVy+t/xq7q/V2kGGSycqmFxa905Vov5R4BE 74KrbBZnm96wW2x6fI3VYsb5fUwWTydcZHNg97hzbQ+bx+Yl9R59W1YxenzeJBfAEsVlk5Ka k1mWWqRvl8CVMf1uD3vBXMOKXcvOszcwntXsYuTkkBAwkTi64AQjhC0mceHeerYuRi4OIYGl jBLvvt9lhHD6mCSOzZzPAlLFJqAp8XfzTTYQW0RAQ2JK12N2kCJmgY1MEpOWrWMCSQgLJEtM 6m8CG8sioCox9+4dZhCbV8BFomv/aRaIdQoSPy+fABvECRT/33kdzBYScJZYM/E44wRG3gWM DKsYRVNLkwuKk9JzDfWKE3OLS/PS9ZLzczcxQoLpyw7GxcesDjEKcDAq8fBy9GgECbEmlhVX 5h5ilOBgVhLhFdfQDBLiTUmsrEotyo8vKs1JLT7EyMTBKdXAqB/TUi1u+kbriLh329xliXYa K7gfMgp1bvH82v3RYpV9r5Bb0/+V2T83bzy9ZcOfJAbu5btu5rpWBx76U6foZ+n85+Ct9TOz d0bnLzV+WFFRU+W7q2YGX6KviorgJ9etJuff/1aTfbEhMzT68dO9tlM3nNX+EG/3u37atg6b j20dT9Z9tdmlrcRSnJFoqMVcVJwIADS1hqIEAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos5440.c | 81 +++++++++++++++--------------------- 1 file changed, 34 insertions(+), 47 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5440.c b/drivers/clk/samsung/clk-exynos5440.c index 4ef38e0..7a08b2d 100644 --- a/drivers/clk/samsung/clk-exynos5440.c +++ b/drivers/clk/samsung/clk-exynos5440.c @@ -9,6 +9,7 @@ * Common Clock Framework support for Exynos5440 SoC. */ +#include #include #include #include @@ -22,79 +23,65 @@ #define CPU_CLK_STATUS 0xfc #define MISC_DOUT1 0x558 -/* - * Let each supported clock get a unique id. This id is used to lookup the clock - * for device tree based platforms. - */ -enum exynos5440_clks { - none, xtal, arm_clk, - - spi_baud = 16, pb0_250, pr0_250, pr1_250, b_250, b_125, b_200, sata, - usb, gmac0, cs250, pb0_250_o, pr0_250_o, pr1_250_o, b_250_o, b_125_o, - b_200_o, sata_o, usb_o, gmac0_o, cs250_o, - - nr_clks, -}; - /* parent clock name list */ PNAME(mout_armclk_p) = { "cplla", "cpllb" }; PNAME(mout_spi_p) = { "div125", "div200" }; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos5440_fixed_rate_ext_clks[] __initdata = { - FRATE(none, "xtal", NULL, CLK_IS_ROOT, 0), + FRATE(0, "xtal", NULL, CLK_IS_ROOT, 0), }; /* fixed rate clocks */ static struct samsung_fixed_rate_clock exynos5440_fixed_rate_clks[] __initdata = { - FRATE(none, "ppll", NULL, CLK_IS_ROOT, 1000000000), - FRATE(none, "usb_phy0", NULL, CLK_IS_ROOT, 60000000), - FRATE(none, "usb_phy1", NULL, CLK_IS_ROOT, 60000000), - FRATE(none, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000), - FRATE(none, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000), + FRATE(0, "ppll", NULL, CLK_IS_ROOT, 1000000000), + FRATE(0, "usb_phy0", NULL, CLK_IS_ROOT, 60000000), + FRATE(0, "usb_phy1", NULL, CLK_IS_ROOT, 60000000), + FRATE(0, "usb_ohci12", NULL, CLK_IS_ROOT, 12000000), + FRATE(0, "usb_ohci48", NULL, CLK_IS_ROOT, 48000000), }; /* fixed factor clocks */ static struct samsung_fixed_factor_clock exynos5440_fixed_factor_clks[] __initdata = { - FFACTOR(none, "div250", "ppll", 1, 4, 0), - FFACTOR(none, "div200", "ppll", 1, 5, 0), - FFACTOR(none, "div125", "div250", 1, 2, 0), + FFACTOR(0, "div250", "ppll", 1, 4, 0), + FFACTOR(0, "div200", "ppll", 1, 5, 0), + FFACTOR(0, "div125", "div250", 1, 2, 0), }; /* mux clocks */ static struct samsung_mux_clock exynos5440_mux_clks[] __initdata = { - MUX(none, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), - MUX_A(arm_clk, "arm_clk", mout_armclk_p, + MUX(0, "mout_spi", mout_spi_p, MISC_DOUT1, 5, 1), + MUX_A(CLK_ARM_CLK, "arm_clk", mout_armclk_p, CPU_CLK_STATUS, 0, 1, "armclk"), }; /* divider clocks */ static struct samsung_div_clock exynos5440_div_clks[] __initdata = { - DIV(spi_baud, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), + DIV(CLK_SPI_BAUD, "div_spi", "mout_spi", MISC_DOUT1, 3, 2), }; /* gate clocks */ static struct samsung_gate_clock exynos5440_gate_clks[] __initdata = { - GATE(pb0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), - GATE(pr0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), - GATE(pr1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), - GATE(b_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0), - GATE(b_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0), - GATE(b_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0), - GATE(sata, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0), - GATE(usb, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0), - GATE(gmac0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0), - GATE(cs250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0), - GATE(pb0_250_o, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0), - GATE(pr0_250_o, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0), - GATE(pr1_250_o, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0), - GATE(b_250_o, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0), - GATE(b_125_o, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0), - GATE(b_200_o, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0), - GATE(sata_o, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0), - GATE(usb_o, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0), - GATE(gmac0_o, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0), - GATE(cs250_o, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), + GATE(CLK_PB0_250, "pb0_250", "div250", CLKEN_OV_VAL, 3, 0, 0), + GATE(CLK_PR0_250, "pr0_250", "div250", CLKEN_OV_VAL, 4, 0, 0), + GATE(CLK_PR1_250, "pr1_250", "div250", CLKEN_OV_VAL, 5, 0, 0), + GATE(CLK_B_250, "b_250", "div250", CLKEN_OV_VAL, 9, 0, 0), + GATE(CLK_B_125, "b_125", "div125", CLKEN_OV_VAL, 10, 0, 0), + GATE(CLK_B_200, "b_200", "div200", CLKEN_OV_VAL, 11, 0, 0), + GATE(CLK_SATA, "sata", "div200", CLKEN_OV_VAL, 12, 0, 0), + GATE(CLK_USB, "usb", "div200", CLKEN_OV_VAL, 13, 0, 0), + GATE(CLK_GMAC0, "gmac0", "div200", CLKEN_OV_VAL, 14, 0, 0), + GATE(CLK_CS250, "cs250", "div250", CLKEN_OV_VAL, 19, 0, 0), + GATE(CLK_PB0_250_O, "pb0_250_o", "pb0_250", CLKEN_OV_VAL, 3, 0, 0), + GATE(CLK_PR0_250_O, "pr0_250_o", "pr0_250", CLKEN_OV_VAL, 4, 0, 0), + GATE(CLK_PR1_250_O, "pr1_250_o", "pr1_250", CLKEN_OV_VAL, 5, 0, 0), + GATE(CLK_B_250_O, "b_250_o", "b_250", CLKEN_OV_VAL, 9, 0, 0), + GATE(CLK_B_125_O, "b_125_o", "b_125", CLKEN_OV_VAL, 10, 0, 0), + GATE(CLK_B_200_O, "b_200_o", "b_200", CLKEN_OV_VAL, 11, 0, 0), + GATE(CLK_SATA_O, "sata_o", "sata", CLKEN_OV_VAL, 12, 0, 0), + GATE(CLK_USB_O, "usb_o", "usb", CLKEN_OV_VAL, 13, 0, 0), + GATE(CLK_GMAC0_O, "gmac0_o", "gmac", CLKEN_OV_VAL, 14, 0, 0), + GATE(CLK_CS250_O, "cs250_o", "cs250", CLKEN_OV_VAL, 19, 0, 0), }; static struct of_device_id ext_clk_match[] __initdata = { @@ -114,7 +101,7 @@ static void __init exynos5440_clk_init(struct device_node *np) return; } - samsung_clk_init(np, reg_base, nr_clks, NULL, 0, NULL, 0); + samsung_clk_init(np, reg_base, CLK_NR_CLKS, NULL, 0, NULL, 0); samsung_clk_of_register_fixed_ext(exynos5440_fixed_rate_ext_clks, ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);