From patchwork Fri Sep 6 10:12:32 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 2854470 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AB2AD9F494 for ; Fri, 6 Sep 2013 10:14:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 28BC8202B1 for ; Fri, 6 Sep 2013 10:14:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4DAE2202B3 for ; Fri, 6 Sep 2013 10:14:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751149Ab3IFKOV (ORCPT ); Fri, 6 Sep 2013 06:14:21 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:15068 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750966Ab3IFKOT (ORCPT ); Fri, 6 Sep 2013 06:14:19 -0400 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MSP009PE8FSRP50@mailout1.w1.samsung.com>; Fri, 06 Sep 2013 11:14:16 +0100 (BST) X-AuditID: cbfec7f4-b7f0a6d000007b1b-d6-5229aaf87eed Received: from eusync3.samsung.com ( [203.254.199.213]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id 7E.64.31515.8FAA9225; Fri, 06 Sep 2013 11:14:16 +0100 (BST) Received: from AMDC1061.digital.local ([106.116.147.88]) by eusync3.samsung.com (Oracle Communications Messaging Server 7u4-23.01 (7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0MSP00I458FJKX90@eusync3.samsung.com>; Fri, 06 Sep 2013 11:14:16 +0100 (BST) From: Andrzej Hajda To: linux-arm-kernel@lists.infradead.org Cc: Andrzej Hajda , Kukjin Kim , Mike Turquette , Kyungmin Park , devicetree@vger.kernel.org (moderated list:OPEN FIRMWARE AND...), linux-samsung-soc@vger.kernel.org (moderated list:ARM/S5P EXYNOS AR...) Subject: [PATCH v2 03/12] clk: exynos4: replace clock ID private enums with IDs from DT header Date: Fri, 06 Sep 2013 12:12:32 +0200 Message-id: <1378462361-13680-4-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 1.8.1.2 In-reply-to: <1378462361-13680-1-git-send-email-a.hajda@samsung.com> References: <1378462361-13680-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrEJMWRmVeSWpSXmKPExsVy+t/xq7o/VmkGGez9w2Jxa905Vov5R4BE 74KrbBZnm96wW2x6fI3VYsb5fUwWTydcZHNg97hzbQ+bx+Yl9R59W1YxenzeJBfAEsVlk5Ka k1mWWqRvl8CVMfXtKsaCX7eZK7bNVW5g3DaLuYuRk0NCwERiz8lGNghbTOLCvfVANheHkMBS RonLxw8xQTh9TBJHT95jAaliE9CU+Lv5JliHiICGxJSux+wgRcwCG5kkJi1bxwSSEBZIkLje uAHMZhFQlVh64g9YM6+As8Tc/3fZIdYpSPy8fAJsEKeAi8T/zutgthBQzZqJxxknMPIuYGRY xSiaWppcUJyUnmuoV5yYW1yal66XnJ+7iRESTl92MC4+ZnWIUYCDUYmHl6NHI0iINbGsuDL3 EKMEB7OSCK+4hmaQEG9KYmVValF+fFFpTmrxIUYmDk6pBkb7vuPbVx6QP/bb8PikT885Zqit W7T554X6mA0VXzgaTD671SsEL5+0LsXylV/BrLQ9yq+fuDQvUEq4rvjgod7LBrvHK7S02eZ/ 35/2foH+TR73IGF3mSRuIYHPJdyvP13Ojsg0byq9GHjg/YRfDVtdu5QX8Ohc35HBc7KgY1tT 8acDBkkPE0KVWIozEg21mIuKEwEvL1iSBQIAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch replaces private enum clock IDs in the driver with macros provided by the DT header. Signed-off-by: Andrzej Hajda Signed-off-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos4.c | 857 ++++++++++++++++++-------------------- 1 file changed, 406 insertions(+), 451 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 742b4c5..1e93004 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -10,6 +10,7 @@ * Common Clock Framework support for all Exynos4 SoCs. */ +#include #include #include #include @@ -129,68 +130,6 @@ enum exynos4_plls { }; /* - * Let each supported clock get a unique id. This id is used to lookup the clock - * for device tree based platforms. The clocks are categorized into three - * sections: core, sclk gate and bus interface gate clocks. - * - * When adding a new clock to this list, it is advised to choose a clock - * category and add it to the end of that category. That is because the the - * device tree source file is referring to these ids and any change in the - * sequence number of existing clocks will require corresponding change in the - * device tree files. This limitation would go away when pre-processor support - * for dtc would be available. - */ -enum exynos4_clks { - none, - - /* core clocks */ - xxti, xusbxti, fin_pll, fout_apll, fout_mpll, fout_epll, fout_vpll, - sclk_apll, sclk_mpll, sclk_epll, sclk_vpll, arm_clk, aclk200, aclk100, - aclk160, aclk133, mout_mpll_user_t, mout_mpll_user_c, mout_core, - mout_apll, /* 20 */ - - /* gate for special clocks (sclk) */ - sclk_fimc0 = 128, sclk_fimc1, sclk_fimc2, sclk_fimc3, sclk_cam0, - sclk_cam1, sclk_csis0, sclk_csis1, sclk_hdmi, sclk_mixer, sclk_dac, - sclk_pixel, sclk_fimd0, sclk_mdnie0, sclk_mdnie_pwm0, sclk_mipi0, - sclk_audio0, sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_mmc4, - sclk_sata, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_uart4, - sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, - sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1, - sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp, - sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d, - - /* gate clocks */ - fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0, - smmu_fimc1, smmu_fimc2, smmu_fimc3, smmu_jpeg, vp, mixer, tvenc, hdmi, - smmu_tv, mfc, smmu_mfcl, smmu_mfcr, g3d, g2d, rotator, mdma, smmu_g2d, - smmu_rotator, smmu_mdma, fimd0, mie0, mdnie0, dsim0, smmu_fimd0, fimd1, - mie1, dsim1, smmu_fimd1, pdma0, pdma1, pcie_phy, sata_phy, tsi, sdmmc0, - sdmmc1, sdmmc2, sdmmc3, sdmmc4, sata, sromc, usb_host, usb_device, pcie, - onenand, nfcon, smmu_pcie, gps, smmu_gps, uart0, uart1, uart2, uart3, - uart4, i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c_hdmi, tsadc, - spi0, spi1, spi2, i2s1, i2s2, pcm0, i2s0, pcm1, pcm2, pwm, slimbus, - spdif, ac97, modemif, chipid, sysreg, hdmi_cec, mct, wdt, rtc, keyif, - audss, mipi_hsi, mdma2, pixelasyncm0, pixelasyncm1, fimc_lite0, - fimc_lite1, ppmuispx, ppmuispmx, fimc_isp, fimc_drc, fimc_fd, mcuisp, - gicisp, smmu_isp, smmu_drc, smmu_fd, smmu_lite0, smmu_lite1, mcuctl_isp, - mpwm_isp, i2c0_isp, i2c1_isp, mtcadc_isp, pwm_isp, wdt_isp, uart_isp, - asyncaxim, smmu_ispcx, spi0_isp, spi1_isp, pwm_isp_sclk, spi0_isp_sclk, - spi1_isp_sclk, uart_isp_sclk, tmu_apbif, - - /* mux clocks */ - mout_fimc0 = 384, mout_fimc1, mout_fimc2, mout_fimc3, mout_cam0, - mout_cam1, mout_csis0, mout_csis1, mout_g3d0, mout_g3d1, mout_g3d, - aclk400_mcuisp, - - /* div clocks */ - div_isp0 = 450, div_isp1, div_mcuisp0, div_mcuisp1, div_aclk200, - div_aclk400_mcuisp, - - nr_clks, -}; - -/* * list of controller registers to be saved and restored during a * suspend/resume cycle. */ @@ -346,254 +285,258 @@ PNAME(mout_user_aclk266_gps_p4x12) = {"fin_pll", "div_aclk266_gps", }; /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock exynos4_fixed_rate_ext_clks[] __initdata = { - FRATE(xxti, "xxti", NULL, CLK_IS_ROOT, 0), - FRATE(xusbxti, "xusbxti", NULL, CLK_IS_ROOT, 0), + FRATE(CLK_XXTI, "xxti", NULL, CLK_IS_ROOT, 0), + FRATE(CLK_XUSBXTI, "xusbxti", NULL, CLK_IS_ROOT, 0), }; /* fixed rate clocks generated inside the soc */ static struct samsung_fixed_rate_clock exynos4_fixed_rate_clks[] __initdata = { - FRATE(none, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), - FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), - FRATE(none, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), + FRATE(0, "sclk_hdmi24m", NULL, CLK_IS_ROOT, 24000000), + FRATE(0, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 27000000), + FRATE(0, "sclk_usbphy0", NULL, CLK_IS_ROOT, 48000000), }; static struct samsung_fixed_rate_clock exynos4210_fixed_rate_clks[] __initdata = { - FRATE(none, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), + FRATE(0, "sclk_usbphy1", NULL, CLK_IS_ROOT, 48000000), }; /* list of mux clocks supported in all exynos4 soc's */ static struct samsung_mux_clock exynos4_mux_clks[] __initdata = { - MUX_FA(mout_apll, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, + MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, CLK_SET_RATE_PARENT, 0, "mout_apll"), - MUX(none, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), - MUX(none, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), - MUX(none, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), - MUX_F(mout_g3d1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, + MUX(0, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1), + MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1), + MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1), + MUX_F(CLK_MOUT_G3D1, "mout_g3d1", sclk_evpll_p, SRC_G3D, 4, 1, CLK_SET_RATE_PARENT, 0), - MUX_F(mout_g3d, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, + MUX_F(CLK_MOUT_G3D, "mout_g3d", mout_g3d_p, SRC_G3D, 8, 1, CLK_SET_RATE_PARENT, 0), - MUX(none, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), - MUX(none, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), - MUX_A(sclk_epll, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, "sclk_epll"), - MUX(none, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), + MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIL1, 8, 2), + MUX(0, "mout_onenand1", mout_onenand1_p, SRC_TOP0, 0, 1), + MUX_A(CLK_SCLK_EPLL, "sclk_epll", mout_epll_p, SRC_TOP0, 4, 1, + "sclk_epll"), + MUX(0, "mout_onenand", mout_onenand_p, SRC_TOP0, 28, 1), }; /* list of mux clocks supported in exynos4210 soc */ static struct samsung_mux_clock exynos4210_mux_clks[] __initdata = { - MUX(none, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), - MUX(none, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), - MUX(none, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), - MUX(none, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), - MUX(none, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), - MUX(none, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), - MUX(none, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), - MUX(none, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), - MUX(none, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), - MUX(none, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), - MUX(none, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), - MUX(none, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), - MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "mout_mpll"), - MUX_A(mout_core, "mout_core", mout_core_p4210, + MUX(0, "mout_aclk200", sclk_ampll_p4210, SRC_TOP0, 12, 1), + MUX(0, "mout_aclk100", sclk_ampll_p4210, SRC_TOP0, 16, 1), + MUX(0, "mout_aclk160", sclk_ampll_p4210, SRC_TOP0, 20, 1), + MUX(0, "mout_aclk133", sclk_ampll_p4210, SRC_TOP0, 24, 1), + MUX(0, "mout_vpllsrc", mout_vpllsrc_p, SRC_TOP1, 0, 1), + MUX(0, "mout_mixer", mout_mixer_p4210, SRC_TV, 4, 1), + MUX(0, "mout_dac", mout_dac_p4210, SRC_TV, 8, 1), + MUX(0, "mout_g2d0", sclk_ampll_p4210, E4210_SRC_IMAGE, 0, 1), + MUX(0, "mout_g2d1", sclk_evpll_p, E4210_SRC_IMAGE, 4, 1), + MUX(0, "mout_g2d", mout_g2d_p, E4210_SRC_IMAGE, 8, 1), + MUX(0, "mout_fimd1", group1_p4210, E4210_SRC_LCD1, 0, 4), + MUX(0, "mout_mipi1", group1_p4210, E4210_SRC_LCD1, 12, 4), + MUX_A(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, + "mout_mpll"), + MUX_A(CLK_MOUT_CORE, "mout_core", mout_core_p4210, SRC_CPU, 16, 1, "moutcore"), - MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210, + MUX_A(CLK_SCLK_VPLL, "sclk_vpll", sclk_vpll_p4210, SRC_TOP0, 8, 1, "sclk_vpll"), - MUX(mout_fimc0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), - MUX(mout_fimc1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), - MUX(mout_fimc2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), - MUX(mout_fimc3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), - MUX(mout_cam0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), - MUX(mout_cam1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), - MUX(mout_csis0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), - MUX(mout_csis1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), - MUX(none, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), - MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, + MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4), + MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4210, SRC_CAM, 4, 4), + MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4210, SRC_CAM, 8, 4), + MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4210, SRC_CAM, 12, 4), + MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4210, SRC_CAM, 16, 4), + MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4210, SRC_CAM, 20, 4), + MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4210, SRC_CAM, 24, 4), + MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4210, SRC_CAM, 28, 4), + MUX(0, "mout_mfc0", sclk_ampll_p4210, SRC_MFC, 0, 1), + MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4210, SRC_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), - MUX(none, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), - MUX(none, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), - MUX(none, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), - MUX(none, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), - MUX(none, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), - MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), - MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), - MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), - MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), - MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), - MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), - MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), - MUX(none, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), - MUX(none, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), - MUX(none, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), - MUX(none, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), - MUX(none, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), - MUX(none, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), - MUX(none, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), + MUX(0, "mout_fimd0", group1_p4210, SRC_LCD0, 0, 4), + MUX(0, "mout_mipi0", group1_p4210, SRC_LCD0, 12, 4), + MUX(0, "mout_audio0", mout_audio0_p4210, SRC_MAUDIO, 0, 4), + MUX(0, "mout_mmc0", group1_p4210, SRC_FSYS, 0, 4), + MUX(0, "mout_mmc1", group1_p4210, SRC_FSYS, 4, 4), + MUX(0, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4), + MUX(0, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4), + MUX(0, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4), + MUX(0, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1), + MUX(0, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4), + MUX(0, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4), + MUX(0, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4), + MUX(0, "mout_uart3", group1_p4210, SRC_PERIL0, 12, 4), + MUX(0, "mout_uart4", group1_p4210, SRC_PERIL0, 16, 4), + MUX(0, "mout_audio1", mout_audio1_p4210, SRC_PERIL1, 0, 4), + MUX(0, "mout_audio2", mout_audio2_p4210, SRC_PERIL1, 4, 4), + MUX(0, "mout_spi0", group1_p4210, SRC_PERIL1, 16, 4), + MUX(0, "mout_spi1", group1_p4210, SRC_PERIL1, 20, 4), + MUX(0, "mout_spi2", group1_p4210, SRC_PERIL1, 24, 4), }; /* list of mux clocks supported in exynos4x12 soc */ static struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { - MUX_A(mout_mpll_user_c, "mout_mpll_user_c", mout_mpll_user_p4x12, + MUX_A(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p4x12, SRC_CPU, 24, 1, "mout_mpll"), - MUX(none, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), - MUX(none, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), - MUX(mout_mpll_user_t, "mout_mpll_user_t", mout_mpll_user_p4x12, + MUX(0, "mout_aclk266_gps", aclk_p4412, SRC_TOP1, 4, 1), + MUX(0, "mout_aclk400_mcuisp", aclk_p4412, SRC_TOP1, 8, 1), + MUX(CLK_MOUT_MPLL_USER_T, "mout_mpll_user_t", mout_mpll_user_p4x12, SRC_TOP1, 12, 1), - MUX(none, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, + MUX(0, "mout_user_aclk266_gps", mout_user_aclk266_gps_p4x12, SRC_TOP1, 16, 1), - MUX(aclk200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), - MUX(aclk400_mcuisp, "aclk400_mcuisp", mout_user_aclk400_mcuisp_p4x12, - SRC_TOP1, 24, 1), - MUX(none, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), - MUX(none, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), - MUX(none, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), - MUX(none, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), - MUX(none, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), - MUX(none, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), - MUX(none, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), - MUX(none, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), - MUX(none, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), - MUX(none, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), - MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, + MUX(CLK_ACLK200, "aclk200", mout_user_aclk200_p4x12, SRC_TOP1, 20, 1), + MUX(CLK_ACLK400_MCUISP, "aclk400_mcuisp", + mout_user_aclk400_mcuisp_p4x12, SRC_TOP1, 24, 1), + MUX(0, "mout_aclk200", aclk_p4412, SRC_TOP0, 12, 1), + MUX(0, "mout_aclk100", aclk_p4412, SRC_TOP0, 16, 1), + MUX(0, "mout_aclk160", aclk_p4412, SRC_TOP0, 20, 1), + MUX(0, "mout_aclk133", aclk_p4412, SRC_TOP0, 24, 1), + MUX(0, "mout_mdnie0", group1_p4x12, SRC_LCD0, 4, 4), + MUX(0, "mout_mdnie_pwm0", group1_p4x12, SRC_LCD0, 8, 4), + MUX(0, "mout_sata", sclk_ampll_p4x12, SRC_FSYS, 24, 1), + MUX(0, "mout_jpeg0", sclk_ampll_p4x12, E4X12_SRC_CAM1, 0, 1), + MUX(0, "mout_jpeg1", sclk_evpll_p, E4X12_SRC_CAM1, 4, 1), + MUX(0, "mout_jpeg", mout_jpeg_p, E4X12_SRC_CAM1, 8, 1), + MUX_A(CLK_SCLK_MPLL, "sclk_mpll", mout_mpll_p, SRC_DMC, 12, 1, "sclk_mpll"), - MUX_A(sclk_vpll, "sclk_vpll", mout_vpll_p, + MUX_A(CLK_SCLK_VPLL, "sclk_vpll", mout_vpll_p, SRC_TOP0, 8, 1, "sclk_vpll"), - MUX_A(mout_core, "mout_core", mout_core_p4x12, + MUX_A(CLK_MOUT_CORE, "mout_core", mout_core_p4x12, SRC_CPU, 16, 1, "moutcore"), - MUX(mout_fimc0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), - MUX(mout_fimc1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), - MUX(mout_fimc2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), - MUX(mout_fimc3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), - MUX(mout_cam0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), - MUX(mout_cam1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), - MUX(mout_csis0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), - MUX(mout_csis1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), - MUX(none, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), - MUX_F(mout_g3d0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, + MUX(CLK_MOUT_FIMC0, "mout_fimc0", group1_p4x12, SRC_CAM, 0, 4), + MUX(CLK_MOUT_FIMC1, "mout_fimc1", group1_p4x12, SRC_CAM, 4, 4), + MUX(CLK_MOUT_FIMC2, "mout_fimc2", group1_p4x12, SRC_CAM, 8, 4), + MUX(CLK_MOUT_FIMC3, "mout_fimc3", group1_p4x12, SRC_CAM, 12, 4), + MUX(CLK_MOUT_CAM0, "mout_cam0", group1_p4x12, SRC_CAM, 16, 4), + MUX(CLK_MOUT_CAM1, "mout_cam1", group1_p4x12, SRC_CAM, 20, 4), + MUX(CLK_MOUT_CSIS0, "mout_csis0", group1_p4x12, SRC_CAM, 24, 4), + MUX(CLK_MOUT_CSIS1, "mout_csis1", group1_p4x12, SRC_CAM, 28, 4), + MUX(0, "mout_mfc0", sclk_ampll_p4x12, SRC_MFC, 0, 1), + MUX_F(CLK_MOUT_G3D0, "mout_g3d0", sclk_ampll_p4x12, SRC_G3D, 0, 1, CLK_SET_RATE_PARENT, 0), - MUX(none, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), - MUX(none, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), - MUX(none, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), - MUX(none, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), - MUX(none, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), - MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), - MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), - MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), - MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), - MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), - MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), - MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), - MUX(none, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), - MUX(none, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), - MUX(none, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), - MUX(none, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), - MUX(none, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), - MUX(none, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), - MUX(none, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), - MUX(none, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), - MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), - MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), - MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), - MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), - MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), - MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), + MUX(0, "mout_fimd0", group1_p4x12, SRC_LCD0, 0, 4), + MUX(0, "mout_mipi0", group1_p4x12, SRC_LCD0, 12, 4), + MUX(0, "mout_audio0", mout_audio0_p4x12, SRC_MAUDIO, 0, 4), + MUX(0, "mout_mmc0", group1_p4x12, SRC_FSYS, 0, 4), + MUX(0, "mout_mmc1", group1_p4x12, SRC_FSYS, 4, 4), + MUX(0, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), + MUX(0, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), + MUX(0, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), + MUX(0, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), + MUX(0, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), + MUX(0, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), + MUX(0, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), + MUX(0, "mout_uart3", group1_p4x12, SRC_PERIL0, 12, 4), + MUX(0, "mout_uart4", group1_p4x12, SRC_PERIL0, 16, 4), + MUX(0, "mout_audio1", mout_audio1_p4x12, SRC_PERIL1, 0, 4), + MUX(0, "mout_audio2", mout_audio2_p4x12, SRC_PERIL1, 4, 4), + MUX(0, "mout_spi0", group1_p4x12, SRC_PERIL1, 16, 4), + MUX(0, "mout_spi1", group1_p4x12, SRC_PERIL1, 20, 4), + MUX(0, "mout_spi2", group1_p4x12, SRC_PERIL1, 24, 4), + MUX(0, "mout_pwm_isp", group1_p4x12, E4X12_SRC_ISP, 0, 4), + MUX(0, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4), + MUX(0, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4), + MUX(0, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4), + MUX(0, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1), + MUX(0, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1), + MUX(0, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1), }; /* list of divider clocks supported in all exynos4 soc's */ static struct samsung_div_clock exynos4_div_clks[] __initdata = { - DIV(none, "div_core", "mout_core", DIV_CPU0, 0, 3), - DIV(none, "div_core2", "div_core", DIV_CPU0, 28, 3), - DIV(none, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), - DIV(none, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), - DIV(none, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), - DIV(none, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), - DIV(none, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), - DIV(none, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), - DIV(none, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), - DIV(none, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), - DIV(sclk_mfc, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), - DIV_F(none, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, + DIV(0, "div_core", "mout_core", DIV_CPU0, 0, 3), + DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3), + DIV(0, "div_fimc0", "mout_fimc0", DIV_CAM, 0, 4), + DIV(0, "div_fimc1", "mout_fimc1", DIV_CAM, 4, 4), + DIV(0, "div_fimc2", "mout_fimc2", DIV_CAM, 8, 4), + DIV(0, "div_fimc3", "mout_fimc3", DIV_CAM, 12, 4), + DIV(0, "div_cam0", "mout_cam0", DIV_CAM, 16, 4), + DIV(0, "div_cam1", "mout_cam1", DIV_CAM, 20, 4), + DIV(0, "div_csis0", "mout_csis0", DIV_CAM, 24, 4), + DIV(0, "div_csis1", "mout_csis1", DIV_CAM, 28, 4), + DIV(CLK_SCLK_MFC, "sclk_mfc", "mout_mfc", DIV_MFC, 0, 4), + DIV_F(0, "div_g3d", "mout_g3d", DIV_G3D, 0, 4, CLK_SET_RATE_PARENT, 0), - DIV(none, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), - DIV(none, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), - DIV(none, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), - DIV(sclk_pcm0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), - DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), - DIV(none, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), - DIV(none, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), - DIV(none, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), - DIV(sclk_pixel, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), - DIV(aclk100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), - DIV(aclk160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), - DIV(aclk133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), - DIV(none, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), - DIV(sclk_slimbus, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), - DIV(sclk_pcm1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), - DIV(sclk_pcm2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), - DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), - DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), - DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), - DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), - DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), - DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), - DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), - DIV(none, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), - DIV(none, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), - DIV(none, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), - DIV(none, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), - DIV(none, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), - DIV(none, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), - DIV(none, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), - DIV(none, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), - DIV(none, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), - DIV(none, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), - DIV_A(arm_clk, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "armclk"), - DIV_A(sclk_apll, "sclk_apll", "mout_apll", + DIV(0, "div_fimd0", "mout_fimd0", DIV_LCD0, 0, 4), + DIV(0, "div_mipi0", "mout_mipi0", DIV_LCD0, 16, 4), + DIV(0, "div_audio0", "mout_audio0", DIV_MAUDIO, 0, 4), + DIV(CLK_SCLK_PCM0, "sclk_pcm0", "sclk_audio0", DIV_MAUDIO, 4, 8), + DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), + DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4), + DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), + DIV(0, "div_mmc3", "mout_mmc3", DIV_FSYS2, 16, 4), + DIV(CLK_SCLK_PIXEL, "sclk_pixel", "sclk_vpll", DIV_TV, 0, 4), + DIV(CLK_ACLK100, "aclk100", "mout_aclk100", DIV_TOP, 4, 4), + DIV(CLK_ACLK160, "aclk160", "mout_aclk160", DIV_TOP, 8, 3), + DIV(CLK_ACLK133, "aclk133", "mout_aclk133", DIV_TOP, 12, 3), + DIV(0, "div_onenand", "mout_onenand1", DIV_TOP, 16, 3), + DIV(CLK_SCLK_SLIMBUS, "sclk_slimbus", "sclk_epll", DIV_PERIL3, 4, 4), + DIV(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_audio1", DIV_PERIL4, 4, 8), + DIV(CLK_SCLK_PCM2, "sclk_pcm2", "sclk_audio2", DIV_PERIL4, 20, 8), + DIV(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), + DIV(CLK_SCLK_I2S2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), + DIV(0, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), + DIV(0, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), + DIV(0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), + DIV(0, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), + DIV(0, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), + DIV(0, "div_uart3", "mout_uart3", DIV_PERIL0, 12, 4), + DIV(0, "div_uart4", "mout_uart4", DIV_PERIL0, 16, 4), + DIV(0, "div_spi0", "mout_spi0", DIV_PERIL1, 0, 4), + DIV(0, "div_spi_pre0", "div_spi0", DIV_PERIL1, 8, 8), + DIV(0, "div_spi1", "mout_spi1", DIV_PERIL1, 16, 4), + DIV(0, "div_spi_pre1", "div_spi1", DIV_PERIL1, 24, 8), + DIV(0, "div_spi2", "mout_spi2", DIV_PERIL2, 0, 4), + DIV(0, "div_spi_pre2", "div_spi2", DIV_PERIL2, 8, 8), + DIV(0, "div_audio1", "mout_audio1", DIV_PERIL4, 0, 4), + DIV(0, "div_audio2", "mout_audio2", DIV_PERIL4, 16, 4), + DIV_A(CLK_ARM_CLK, "arm_clk", "div_core2", DIV_CPU0, 28, 3, "armclk"), + DIV_A(CLK_SCLK_APLL, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3, "sclk_apll"), - DIV_F(none, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, + DIV_F(0, "div_mipi_pre0", "div_mipi0", DIV_LCD0, 20, 4, CLK_SET_RATE_PARENT, 0), - DIV_F(none, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, + DIV_F(0, "div_mmc_pre0", "div_mmc0", DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0), - DIV_F(none, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, + DIV_F(0, "div_mmc_pre1", "div_mmc1", DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0), - DIV_F(none, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, + DIV_F(0, "div_mmc_pre2", "div_mmc2", DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0), - DIV_F(none, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, + DIV_F(0, "div_mmc_pre3", "div_mmc3", DIV_FSYS2, 24, 8, CLK_SET_RATE_PARENT, 0), }; /* list of divider clocks supported in exynos4210 soc */ static struct samsung_div_clock exynos4210_div_clks[] __initdata = { - DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), - DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), - DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), - DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), - DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), - DIV_F(none, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, + DIV(CLK_ACLK200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3), + DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4), + DIV(0, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4), + DIV(0, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4), + DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), + DIV_F(0, "div_mipi_pre1", "div_mipi1", E4210_DIV_LCD1, 20, 4, CLK_SET_RATE_PARENT, 0), }; /* list of divider clocks supported in exynos4x12 soc */ static struct samsung_div_clock exynos4x12_div_clks[] __initdata = { - DIV(none, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), - DIV(none, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), - DIV(none, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), - DIV(none, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), - DIV(none, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), - DIV(div_aclk200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), - DIV(none, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), - DIV(div_aclk400_mcuisp, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", + DIV(0, "div_mdnie0", "mout_mdnie0", DIV_LCD0, 4, 4), + DIV(0, "div_mdnie_pwm0", "mout_mdnie_pwm0", DIV_LCD0, 8, 4), + DIV(0, "div_mdnie_pwm_pre0", "div_mdnie_pwm0", DIV_LCD0, 12, 4), + DIV(0, "div_mipihsi", "mout_mipihsi", DIV_FSYS0, 20, 4), + DIV(0, "div_jpeg", "mout_jpeg", E4X12_DIV_CAM1, 0, 4), + DIV(CLK_DIV_ACLK200, "div_aclk200", "mout_aclk200", DIV_TOP, 0, 3), + DIV(0, "div_aclk266_gps", "mout_aclk266_gps", DIV_TOP, 20, 3), + DIV(CLK_DIV_ACLK400_MCUISP, "div_aclk400_mcuisp", "mout_aclk400_mcuisp", DIV_TOP, 24, 3), - DIV(none, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), - DIV(none, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), - DIV(none, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), - DIV(none, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), - DIV(none, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), - DIV(none, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), - DIV(div_isp0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3), - DIV(div_isp1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3), - DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), - DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3), - DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3), - DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), + DIV(0, "div_pwm_isp", "mout_pwm_isp", E4X12_DIV_ISP, 0, 4), + DIV(0, "div_spi0_isp", "mout_spi0_isp", E4X12_DIV_ISP, 4, 4), + DIV(0, "div_spi0_isp_pre", "div_spi0_isp", E4X12_DIV_ISP, 8, 8), + DIV(0, "div_spi1_isp", "mout_spi1_isp", E4X12_DIV_ISP, 16, 4), + DIV(0, "div_spi1_isp_pre", "div_spi1_isp", E4X12_DIV_ISP, 20, 8), + DIV(0, "div_uart_isp", "mout_uart_isp", E4X12_DIV_ISP, 28, 4), + DIV(CLK_DIV_ISP0, "div_isp0", "aclk200", E4X12_DIV_ISP0, 0, 3), + DIV(CLK_DIV_ISP1, "div_isp1", "aclk200", E4X12_DIV_ISP0, 4, 3), + DIV(0, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3), + DIV(CLK_DIV_MCUISP0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, + 3), + DIV(CLK_DIV_MCUISP1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, + 3), + DIV(CLK_SCLK_FIMG2D, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4), }; /* list of gate clocks supported in all exynos4 soc's */ @@ -603,327 +546,339 @@ static struct samsung_gate_clock exynos4_gate_clks[] __initdata = { * the device name and clock alias names specified below for some * of the clocks can be removed. */ - GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), - GATE(sclk_spdif, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, 0), - GATE(jpeg, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), - GATE(mie0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), - GATE(dsim0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), - GATE(fimd1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), - GATE(mie1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), - GATE(dsim1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), - GATE(smmu_fimd1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, 0), - GATE(tsi, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), - GATE(sromc, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), - GATE(sclk_g3d, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, + GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0), + GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif", SRC_MASK_PERIL1, 8, 0, + 0), + GATE(CLK_JPEG, "jpeg", "aclk160", GATE_IP_CAM, 6, 0, 0), + GATE(CLK_MIE0, "mie0", "aclk160", GATE_IP_LCD0, 1, 0, 0), + GATE(CLK_DSIM0, "dsim0", "aclk160", GATE_IP_LCD0, 3, 0, 0), + GATE(CLK_FIMD1, "fimd1", "aclk160", E4210_GATE_IP_LCD1, 0, 0, 0), + GATE(CLK_MIE1, "mie1", "aclk160", E4210_GATE_IP_LCD1, 1, 0, 0), + GATE(CLK_DSIM1, "dsim1", "aclk160", E4210_GATE_IP_LCD1, 3, 0, 0), + GATE(CLK_SMMU_FIMD1, "smmu_fimd1", "aclk160", E4210_GATE_IP_LCD1, 4, 0, + 0), + GATE(CLK_TSI, "tsi", "aclk133", GATE_IP_FSYS, 4, 0, 0), + GATE(CLK_SROMC, "sromc", "aclk133", GATE_IP_FSYS, 11, 0, 0), + GATE(CLK_SCLK_G3D, "sclk_g3d", "div_g3d", GATE_IP_G3D, 0, CLK_SET_RATE_PARENT, 0), - GATE(usb_device, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), - GATE(onenand, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), - GATE(nfcon, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), - GATE(gps, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), - GATE(smmu_gps, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), - GATE(slimbus, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), - GATE(sclk_cam0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, + GATE(CLK_USB_DEVICE, "usb_device", "aclk133", GATE_IP_FSYS, 13, 0, 0), + GATE(CLK_ONENAND, "onenand", "aclk133", GATE_IP_FSYS, 15, 0, 0), + GATE(CLK_NFCON, "nfcon", "aclk133", GATE_IP_FSYS, 16, 0, 0), + GATE(CLK_GPS, "gps", "aclk133", GATE_IP_GPS, 0, 0, 0), + GATE(CLK_SMMU_GPS, "smmu_gps", "aclk133", GATE_IP_GPS, 1, 0, 0), + GATE(CLK_SLIMBUS, "slimbus", "aclk100", GATE_IP_PERIL, 25, 0, 0), + GATE(CLK_SCLK_CAM0, "sclk_cam0", "div_cam0", GATE_SCLK_CAM, 4, CLK_SET_RATE_PARENT, 0), - GATE(sclk_cam1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, + GATE(CLK_SCLK_CAM1, "sclk_cam1", "div_cam1", GATE_SCLK_CAM, 5, CLK_SET_RATE_PARENT, 0), - GATE(sclk_mipi0, "sclk_mipi0", "div_mipi_pre0", + GATE(CLK_SCLK_MIPI0, "sclk_mipi0", "div_mipi_pre0", SRC_MASK_LCD0, 12, CLK_SET_RATE_PARENT, 0), - GATE(sclk_audio0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, + GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_audio0", SRC_MASK_MAUDIO, 0, CLK_SET_RATE_PARENT, 0), - GATE(sclk_audio1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, + GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_audio1", SRC_MASK_PERIL1, 0, CLK_SET_RATE_PARENT, 0), - GATE_D(vp, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0), - GATE_D(mixer, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), - GATE_D(hdmi, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, 0), - GATE_A(pwm, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"), - GATE_A(sdmmc4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"), - GATE_A(usb_host, "usb_host", "aclk133", + GATE_D(CLK_VP, "s5p-mixer", "vp", "aclk160", GATE_IP_TV, 0, 0, 0), + GATE_D(CLK_MIXER, "s5p-mixer", "mixer", "aclk160", GATE_IP_TV, 1, 0, 0), + GATE_D(CLK_HDMI, "exynos4-hdmi", "hdmi", "aclk160", GATE_IP_TV, 3, 0, + 0), + GATE_A(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0, "timers"), + GATE_A(CLK_SDMMC4, "sdmmc4", "aclk133", GATE_IP_FSYS, 9, 0, 0, "biu"), + GATE_A(CLK_USB_HOST, "usb_host", "aclk133", GATE_IP_FSYS, 12, 0, 0, "usbhost"), - GATE_DA(sclk_fimc0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0", + GATE_DA(CLK_SCLK_FIMC0, "exynos4-fimc.0", "sclk_fimc0", "div_fimc0", SRC_MASK_CAM, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), - GATE_DA(sclk_fimc1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1", + GATE_DA(CLK_SCLK_FIMC1, "exynos4-fimc.1", "sclk_fimc1", "div_fimc1", SRC_MASK_CAM, 4, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), - GATE_DA(sclk_fimc2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2", + GATE_DA(CLK_SCLK_FIMC2, "exynos4-fimc.2", "sclk_fimc2", "div_fimc2", SRC_MASK_CAM, 8, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), - GATE_DA(sclk_fimc3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3", + GATE_DA(CLK_SCLK_FIMC3, "exynos4-fimc.3", "sclk_fimc3", "div_fimc3", SRC_MASK_CAM, 12, CLK_SET_RATE_PARENT, 0, "sclk_fimc"), - GATE_DA(sclk_csis0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0", + GATE_DA(CLK_SCLK_CSIS0, "s5p-mipi-csis.0", "sclk_csis0", "div_csis0", SRC_MASK_CAM, 24, CLK_SET_RATE_PARENT, 0, "sclk_csis"), - GATE_DA(sclk_csis1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1", + GATE_DA(CLK_SCLK_CSIS1, "s5p-mipi-csis.1", "sclk_csis1", "div_csis1", SRC_MASK_CAM, 28, CLK_SET_RATE_PARENT, 0, "sclk_csis"), - GATE_DA(sclk_fimd0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0", + GATE_DA(CLK_SCLK_FIMD0, "exynos4-fb.0", "sclk_fimd0", "div_fimd0", SRC_MASK_LCD0, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), - GATE_DA(sclk_mmc0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0", + GATE_DA(CLK_SCLK_MMC0, "exynos4-sdhci.0", "sclk_mmc0", "div_mmc_pre0", SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0, "mmc_busclk.2"), - GATE_DA(sclk_mmc1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1", + GATE_DA(CLK_SCLK_MMC1, "exynos4-sdhci.1", "sclk_mmc1", "div_mmc_pre1", SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0, "mmc_busclk.2"), - GATE_DA(sclk_mmc2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2", + GATE_DA(CLK_SCLK_MMC2, "exynos4-sdhci.2", "sclk_mmc2", "div_mmc_pre2", SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0, "mmc_busclk.2"), - GATE_DA(sclk_mmc3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3", + GATE_DA(CLK_SCLK_MMC3, "exynos4-sdhci.3", "sclk_mmc3", "div_mmc_pre3", SRC_MASK_FSYS, 12, CLK_SET_RATE_PARENT, 0, "mmc_busclk.2"), - GATE_DA(sclk_mmc4, NULL, "sclk_mmc4", "div_mmc_pre4", + GATE_DA(CLK_SCLK_MMC4, NULL, "sclk_mmc4", "div_mmc_pre4", SRC_MASK_FSYS, 16, CLK_SET_RATE_PARENT, 0, "ciu"), - GATE_DA(sclk_uart0, "exynos4210-uart.0", "uclk0", "div_uart0", + GATE_DA(CLK_SCLK_UART0, "exynos4210-uart.0", "uclk0", "div_uart0", SRC_MASK_PERIL0, 0, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), - GATE_DA(sclk_uart1, "exynos4210-uart.1", "uclk1", "div_uart1", + GATE_DA(CLK_SCLK_UART1, "exynos4210-uart.1", "uclk1", "div_uart1", SRC_MASK_PERIL0, 4, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), - GATE_DA(sclk_uart2, "exynos4210-uart.2", "uclk2", "div_uart2", + GATE_DA(CLK_SCLK_UART2, "exynos4210-uart.2", "uclk2", "div_uart2", SRC_MASK_PERIL0, 8, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), - GATE_DA(sclk_uart3, "exynos4210-uart.3", "uclk3", "div_uart3", + GATE_DA(CLK_SCLK_UART3, "exynos4210-uart.3", "uclk3", "div_uart3", SRC_MASK_PERIL0, 12, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), - GATE_DA(sclk_uart4, "exynos4210-uart.4", "uclk4", "div_uart4", + GATE_DA(CLK_SCLK_UART4, "exynos4210-uart.4", "uclk4", "div_uart4", SRC_MASK_PERIL0, 16, CLK_SET_RATE_PARENT, 0, "clk_uart_baud0"), - GATE(sclk_audio2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, + GATE(CLK_SCLK_AUDIO2, "sclk_audio2", "div_audio2", SRC_MASK_PERIL1, 4, CLK_SET_RATE_PARENT, 0), - GATE_DA(sclk_spi0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0", + GATE_DA(CLK_SCLK_SPI0, "exynos4210-spi.0", "sclk_spi0", "div_spi_pre0", SRC_MASK_PERIL1, 16, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), - GATE_DA(sclk_spi1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1", + GATE_DA(CLK_SCLK_SPI1, "exynos4210-spi.1", "sclk_spi1", "div_spi_pre1", SRC_MASK_PERIL1, 20, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), - GATE_DA(sclk_spi2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2", + GATE_DA(CLK_SCLK_SPI2, "exynos4210-spi.2", "sclk_spi2", "div_spi_pre2", SRC_MASK_PERIL1, 24, CLK_SET_RATE_PARENT, 0, "spi_busclk0"), - GATE_DA(fimc0, "exynos4-fimc.0", "fimc0", "aclk160", + GATE_DA(CLK_FIMC0, "exynos4-fimc.0", "fimc0", "aclk160", GATE_IP_CAM, 0, 0, 0, "fimc"), - GATE_DA(fimc1, "exynos4-fimc.1", "fimc1", "aclk160", + GATE_DA(CLK_FIMC1, "exynos4-fimc.1", "fimc1", "aclk160", GATE_IP_CAM, 1, 0, 0, "fimc"), - GATE_DA(fimc2, "exynos4-fimc.2", "fimc2", "aclk160", + GATE_DA(CLK_FIMC2, "exynos4-fimc.2", "fimc2", "aclk160", GATE_IP_CAM, 2, 0, 0, "fimc"), - GATE_DA(fimc3, "exynos4-fimc.3", "fimc3", "aclk160", + GATE_DA(CLK_FIMC3, "exynos4-fimc.3", "fimc3", "aclk160", GATE_IP_CAM, 3, 0, 0, "fimc"), - GATE_DA(csis0, "s5p-mipi-csis.0", "csis0", "aclk160", + GATE_DA(CLK_CSIS0, "s5p-mipi-csis.0", "csis0", "aclk160", GATE_IP_CAM, 4, 0, 0, "fimc"), - GATE_DA(csis1, "s5p-mipi-csis.1", "csis1", "aclk160", + GATE_DA(CLK_CSIS1, "s5p-mipi-csis.1", "csis1", "aclk160", GATE_IP_CAM, 5, 0, 0, "fimc"), - GATE_DA(smmu_fimc0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160", + GATE_DA(CLK_SMMU_FIMC0, "exynos-sysmmu.5", "smmu_fimc0", "aclk160", GATE_IP_CAM, 7, 0, 0, "sysmmu"), - GATE_DA(smmu_fimc1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160", + GATE_DA(CLK_SMMU_FIMC1, "exynos-sysmmu.6", "smmu_fimc1", "aclk160", GATE_IP_CAM, 8, 0, 0, "sysmmu"), - GATE_DA(smmu_fimc2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160", + GATE_DA(CLK_SMMU_FIMC2, "exynos-sysmmu.7", "smmu_fimc2", "aclk160", GATE_IP_CAM, 9, 0, 0, "sysmmu"), - GATE_DA(smmu_fimc3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160", + GATE_DA(CLK_SMMU_FIMC3, "exynos-sysmmu.8", "smmu_fimc3", "aclk160", GATE_IP_CAM, 10, 0, 0, "sysmmu"), - GATE_DA(smmu_jpeg, "exynos-sysmmu.3", "smmu_jpeg", "aclk160", + GATE_DA(CLK_SMMU_JPEG, "exynos-sysmmu.3", "smmu_jpeg", "aclk160", GATE_IP_CAM, 11, 0, 0, "sysmmu"), - GATE(pixelasyncm0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), - GATE(pixelasyncm1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), - GATE_DA(smmu_tv, "exynos-sysmmu.2", "smmu_tv", "aclk160", + GATE(CLK_PIXELASYNCM0, "pxl_async0", "aclk160", GATE_IP_CAM, 17, 0, 0), + GATE(CLK_PIXELASYNCM1, "pxl_async1", "aclk160", GATE_IP_CAM, 18, 0, 0), + GATE_DA(CLK_SMMU_TV, "exynos-sysmmu.2", "smmu_tv", "aclk160", GATE_IP_TV, 4, 0, 0, "sysmmu"), - GATE_DA(mfc, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, "mfc"), - GATE_DA(smmu_mfcl, "exynos-sysmmu.0", "smmu_mfcl", "aclk100", + GATE_DA(CLK_MFC, "s5p-mfc", "mfc", "aclk100", GATE_IP_MFC, 0, 0, 0, + "mfc"), + GATE_DA(CLK_SMMU_MFCL, "exynos-sysmmu.0", "smmu_mfcl", "aclk100", GATE_IP_MFC, 1, 0, 0, "sysmmu"), - GATE_DA(smmu_mfcr, "exynos-sysmmu.1", "smmu_mfcr", "aclk100", + GATE_DA(CLK_SMMU_MFCR, "exynos-sysmmu.1", "smmu_mfcr", "aclk100", GATE_IP_MFC, 2, 0, 0, "sysmmu"), - GATE_DA(fimd0, "exynos4-fb.0", "fimd0", "aclk160", + GATE_DA(CLK_FIMD0, "exynos4-fb.0", "fimd0", "aclk160", GATE_IP_LCD0, 0, 0, 0, "fimd"), - GATE_DA(smmu_fimd0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160", + GATE_DA(CLK_SMMU_FIMD0, "exynos-sysmmu.10", "smmu_fimd0", "aclk160", GATE_IP_LCD0, 4, 0, 0, "sysmmu"), - GATE_DA(pdma0, "dma-pl330.0", "pdma0", "aclk133", + GATE_DA(CLK_PDMA0, "dma-pl330.0", "pdma0", "aclk133", GATE_IP_FSYS, 0, 0, 0, "dma"), - GATE_DA(pdma1, "dma-pl330.1", "pdma1", "aclk133", + GATE_DA(CLK_PDMA1, "dma-pl330.1", "pdma1", "aclk133", GATE_IP_FSYS, 1, 0, 0, "dma"), - GATE_DA(sdmmc0, "exynos4-sdhci.0", "sdmmc0", "aclk133", + GATE_DA(CLK_SDMMC0, "exynos4-sdhci.0", "sdmmc0", "aclk133", GATE_IP_FSYS, 5, 0, 0, "hsmmc"), - GATE_DA(sdmmc1, "exynos4-sdhci.1", "sdmmc1", "aclk133", + GATE_DA(CLK_SDMMC1, "exynos4-sdhci.1", "sdmmc1", "aclk133", GATE_IP_FSYS, 6, 0, 0, "hsmmc"), - GATE_DA(sdmmc2, "exynos4-sdhci.2", "sdmmc2", "aclk133", + GATE_DA(CLK_SDMMC2, "exynos4-sdhci.2", "sdmmc2", "aclk133", GATE_IP_FSYS, 7, 0, 0, "hsmmc"), - GATE_DA(sdmmc3, "exynos4-sdhci.3", "sdmmc3", "aclk133", + GATE_DA(CLK_SDMMC3, "exynos4-sdhci.3", "sdmmc3", "aclk133", GATE_IP_FSYS, 8, 0, 0, "hsmmc"), - GATE_DA(uart0, "exynos4210-uart.0", "uart0", "aclk100", + GATE_DA(CLK_UART0, "exynos4210-uart.0", "uart0", "aclk100", GATE_IP_PERIL, 0, 0, 0, "uart"), - GATE_DA(uart1, "exynos4210-uart.1", "uart1", "aclk100", + GATE_DA(CLK_UART1, "exynos4210-uart.1", "uart1", "aclk100", GATE_IP_PERIL, 1, 0, 0, "uart"), - GATE_DA(uart2, "exynos4210-uart.2", "uart2", "aclk100", + GATE_DA(CLK_UART2, "exynos4210-uart.2", "uart2", "aclk100", GATE_IP_PERIL, 2, 0, 0, "uart"), - GATE_DA(uart3, "exynos4210-uart.3", "uart3", "aclk100", + GATE_DA(CLK_UART3, "exynos4210-uart.3", "uart3", "aclk100", GATE_IP_PERIL, 3, 0, 0, "uart"), - GATE_DA(uart4, "exynos4210-uart.4", "uart4", "aclk100", + GATE_DA(CLK_UART4, "exynos4210-uart.4", "uart4", "aclk100", GATE_IP_PERIL, 4, 0, 0, "uart"), - GATE_DA(i2c0, "s3c2440-i2c.0", "i2c0", "aclk100", + GATE_DA(CLK_I2C0, "s3c2440-i2c.0", "i2c0", "aclk100", GATE_IP_PERIL, 6, 0, 0, "i2c"), - GATE_DA(i2c1, "s3c2440-i2c.1", "i2c1", "aclk100", + GATE_DA(CLK_I2C1, "s3c2440-i2c.1", "i2c1", "aclk100", GATE_IP_PERIL, 7, 0, 0, "i2c"), - GATE_DA(i2c2, "s3c2440-i2c.2", "i2c2", "aclk100", + GATE_DA(CLK_I2C2, "s3c2440-i2c.2", "i2c2", "aclk100", GATE_IP_PERIL, 8, 0, 0, "i2c"), - GATE_DA(i2c3, "s3c2440-i2c.3", "i2c3", "aclk100", + GATE_DA(CLK_I2C3, "s3c2440-i2c.3", "i2c3", "aclk100", GATE_IP_PERIL, 9, 0, 0, "i2c"), - GATE_DA(i2c4, "s3c2440-i2c.4", "i2c4", "aclk100", + GATE_DA(CLK_I2C4, "s3c2440-i2c.4", "i2c4", "aclk100", GATE_IP_PERIL, 10, 0, 0, "i2c"), - GATE_DA(i2c5, "s3c2440-i2c.5", "i2c5", "aclk100", + GATE_DA(CLK_I2C5, "s3c2440-i2c.5", "i2c5", "aclk100", GATE_IP_PERIL, 11, 0, 0, "i2c"), - GATE_DA(i2c6, "s3c2440-i2c.6", "i2c6", "aclk100", + GATE_DA(CLK_I2C6, "s3c2440-i2c.6", "i2c6", "aclk100", GATE_IP_PERIL, 12, 0, 0, "i2c"), - GATE_DA(i2c7, "s3c2440-i2c.7", "i2c7", "aclk100", + GATE_DA(CLK_I2C7, "s3c2440-i2c.7", "i2c7", "aclk100", GATE_IP_PERIL, 13, 0, 0, "i2c"), - GATE_DA(i2c_hdmi, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100", + GATE_DA(CLK_I2C_HDMI, "s3c2440-hdmiphy-i2c", "i2c-hdmi", "aclk100", GATE_IP_PERIL, 14, 0, 0, "i2c"), - GATE_DA(spi0, "exynos4210-spi.0", "spi0", "aclk100", + GATE_DA(CLK_SPI0, "exynos4210-spi.0", "spi0", "aclk100", GATE_IP_PERIL, 16, 0, 0, "spi"), - GATE_DA(spi1, "exynos4210-spi.1", "spi1", "aclk100", + GATE_DA(CLK_SPI1, "exynos4210-spi.1", "spi1", "aclk100", GATE_IP_PERIL, 17, 0, 0, "spi"), - GATE_DA(spi2, "exynos4210-spi.2", "spi2", "aclk100", + GATE_DA(CLK_SPI2, "exynos4210-spi.2", "spi2", "aclk100", GATE_IP_PERIL, 18, 0, 0, "spi"), - GATE_DA(i2s1, "samsung-i2s.1", "i2s1", "aclk100", + GATE_DA(CLK_I2S1, "samsung-i2s.1", "i2s1", "aclk100", GATE_IP_PERIL, 20, 0, 0, "iis"), - GATE_DA(i2s2, "samsung-i2s.2", "i2s2", "aclk100", + GATE_DA(CLK_I2S2, "samsung-i2s.2", "i2s2", "aclk100", GATE_IP_PERIL, 21, 0, 0, "iis"), - GATE_DA(pcm1, "samsung-pcm.1", "pcm1", "aclk100", + GATE_DA(CLK_PCM1, "samsung-pcm.1", "pcm1", "aclk100", GATE_IP_PERIL, 22, 0, 0, "pcm"), - GATE_DA(pcm2, "samsung-pcm.2", "pcm2", "aclk100", + GATE_DA(CLK_PCM2, "samsung-pcm.2", "pcm2", "aclk100", GATE_IP_PERIL, 23, 0, 0, "pcm"), - GATE_DA(spdif, "samsung-spdif", "spdif", "aclk100", + GATE_DA(CLK_SPDIF, "samsung-spdif", "spdif", "aclk100", GATE_IP_PERIL, 26, 0, 0, "spdif"), - GATE_DA(ac97, "samsung-ac97", "ac97", "aclk100", + GATE_DA(CLK_AC97, "samsung-ac97", "ac97", "aclk100", GATE_IP_PERIL, 27, 0, 0, "ac97"), }; /* list of gate clocks supported in exynos4210 soc */ static struct samsung_gate_clock exynos4210_gate_clks[] __initdata = { - GATE(tvenc, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), - GATE(g2d, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), - GATE(rotator, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), - GATE(mdma, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), - GATE(smmu_g2d, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), - GATE(smmu_mdma, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, 0), - GATE(pcie_phy, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), - GATE(sata_phy, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), - GATE(sata, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), - GATE(pcie, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), - GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), - GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), - GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), - GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, + GATE(CLK_TVENC, "tvenc", "aclk160", GATE_IP_TV, 2, 0, 0), + GATE(CLK_G2D, "g2d", "aclk200", E4210_GATE_IP_IMAGE, 0, 0, 0), + GATE(CLK_ROTATOR, "rotator", "aclk200", E4210_GATE_IP_IMAGE, 1, 0, 0), + GATE(CLK_MDMA, "mdma", "aclk200", E4210_GATE_IP_IMAGE, 2, 0, 0), + GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk200", E4210_GATE_IP_IMAGE, 3, 0, 0), + GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4210_GATE_IP_IMAGE, 5, 0, + 0), + GATE(CLK_PCIE_PHY, "pcie_phy", "aclk133", GATE_IP_FSYS, 2, 0, 0), + GATE(CLK_SATA_PHY, "sata_phy", "aclk133", GATE_IP_FSYS, 3, 0, 0), + GATE(CLK_SATA, "sata", "aclk133", GATE_IP_FSYS, 10, 0, 0), + GATE(CLK_PCIE, "pcie", "aclk133", GATE_IP_FSYS, 14, 0, 0), + GATE(CLK_SMMU_PCIE, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0), + GATE(CLK_MODEMIF, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0), + GATE(CLK_CHIPID, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0), + GATE(CLK_SYSREG, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, CLK_IGNORE_UNUSED, 0), - GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0), - GATE(smmu_rotator, "smmu_rotator", "aclk200", + GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, + 0), + GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", E4210_GATE_IP_IMAGE, 4, 0, 0), - GATE(sclk_mipi1, "sclk_mipi1", "div_mipi_pre1", + GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "div_mipi_pre1", E4210_SRC_MASK_LCD1, 12, CLK_SET_RATE_PARENT, 0), - GATE(sclk_sata, "sclk_sata", "div_sata", + GATE(CLK_SCLK_SATA, "sclk_sata", "div_sata", SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), - GATE(sclk_mixer, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), - GATE(sclk_dac, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), - GATE_A(tsadc, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"), - GATE_A(mct, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"), - GATE_A(wdt, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, "watchdog"), - GATE_A(rtc, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"), - GATE_A(keyif, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, "keypad"), - GATE_DA(sclk_fimd1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", + GATE(CLK_SCLK_MIXER, "sclk_mixer", "mout_mixer", SRC_MASK_TV, 4, 0, 0), + GATE(CLK_SCLK_DAC, "sclk_dac", "mout_dac", SRC_MASK_TV, 8, 0, 0), + GATE_A(CLK_TSADC, "tsadc", "aclk100", GATE_IP_PERIL, 15, 0, 0, "adc"), + GATE_A(CLK_MCT, "mct", "aclk100", E4210_GATE_IP_PERIR, 13, 0, 0, "mct"), + GATE_A(CLK_WDT, "watchdog", "aclk100", E4210_GATE_IP_PERIR, 14, 0, 0, + "watchdog"), + GATE_A(CLK_RTC, "rtc", "aclk100", E4210_GATE_IP_PERIR, 15, 0, 0, "rtc"), + GATE_A(CLK_KEYIF, "keyif", "aclk100", E4210_GATE_IP_PERIR, 16, 0, 0, + "keypad"), + GATE_DA(CLK_SCLK_FIMD1, "exynos4-fb.1", "sclk_fimd1", "div_fimd1", E4210_SRC_MASK_LCD1, 0, CLK_SET_RATE_PARENT, 0, "sclk_fimd"), - GATE(tmu_apbif, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, 0), + GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4210_GATE_IP_PERIR, 17, 0, + 0), }; /* list of gate clocks supported in exynos4x12 soc */ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { - GATE(audss, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), - GATE(mdnie0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), - GATE(rotator, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), - GATE(mdma2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), - GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), - GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), - GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), - GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, + GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), + GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), + GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), + GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), + GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, + 0), + GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), + GATE(CLK_CHIPID, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0), + GATE(CLK_SYSREG, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, CLK_IGNORE_UNUSED, 0), - GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0), - GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0", + GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, + 0), + GATE(CLK_SCLK_MDNIE0, "sclk_mdnie0", "div_mdnie0", SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0), - GATE(sclk_mdnie_pwm0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", + GATE(CLK_SCLK_MDNIE_PWM0, "sclk_mdnie_pwm0", "div_mdnie_pwm_pre0", SRC_MASK_LCD0, 8, CLK_SET_RATE_PARENT, 0), - GATE(sclk_mipihsi, "sclk_mipihsi", "div_mipihsi", + GATE(CLK_SCLK_MIPIHSI, "sclk_mipihsi", "div_mipihsi", SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), - GATE(smmu_rotator, "smmu_rotator", "aclk200", + GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "aclk200", E4X12_GATE_IP_IMAGE, 4, 0, 0), - GATE_A(mct, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"), - GATE_A(rtc, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"), - GATE_A(keyif, "keyif", "aclk100", + GATE_A(CLK_MCT, "mct", "aclk100", E4X12_GATE_IP_PERIR, 13, 0, 0, "mct"), + GATE_A(CLK_RTC, "rtc", "aclk100", E4X12_GATE_IP_PERIR, 15, 0, 0, "rtc"), + GATE_A(CLK_KEYIF, "keyif", "aclk100", E4X12_GATE_IP_PERIR, 16, 0, 0, "keypad"), - GATE(sclk_pwm_isp, "sclk_pwm_isp", "div_pwm_isp", + GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "div_pwm_isp", E4X12_SRC_MASK_ISP, 0, CLK_SET_RATE_PARENT, 0), - GATE(sclk_spi0_isp, "sclk_spi0_isp", "div_spi0_isp_pre", + GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "div_spi0_isp_pre", E4X12_SRC_MASK_ISP, 4, CLK_SET_RATE_PARENT, 0), - GATE(sclk_spi1_isp, "sclk_spi1_isp", "div_spi1_isp_pre", + GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "div_spi1_isp_pre", E4X12_SRC_MASK_ISP, 8, CLK_SET_RATE_PARENT, 0), - GATE(sclk_uart_isp, "sclk_uart_isp", "div_uart_isp", + GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "div_uart_isp", E4X12_SRC_MASK_ISP, 12, CLK_SET_RATE_PARENT, 0), - GATE(pwm_isp_sclk, "pwm_isp_sclk", "sclk_pwm_isp", + GATE(CLK_PWM_ISP_SCLK, "pwm_isp_sclk", "sclk_pwm_isp", E4X12_GATE_IP_ISP, 0, 0, 0), - GATE(spi0_isp_sclk, "spi0_isp_sclk", "sclk_spi0_isp", + GATE(CLK_SPI0_ISP_SCLK, "spi0_isp_sclk", "sclk_spi0_isp", E4X12_GATE_IP_ISP, 1, 0, 0), - GATE(spi1_isp_sclk, "spi1_isp_sclk", "sclk_spi1_isp", + GATE(CLK_SPI1_ISP_SCLK, "spi1_isp_sclk", "sclk_spi1_isp", E4X12_GATE_IP_ISP, 2, 0, 0), - GATE(uart_isp_sclk, "uart_isp_sclk", "sclk_uart_isp", + GATE(CLK_UART_ISP_SCLK, "uart_isp_sclk", "sclk_uart_isp", E4X12_GATE_IP_ISP, 3, 0, 0), - GATE_A(wdt, "watchdog", "aclk100", + GATE_A(CLK_WDT, "watchdog", "aclk100", E4X12_GATE_IP_PERIR, 14, 0, 0, "watchdog"), - GATE_DA(pcm0, "samsung-pcm.0", "pcm0", "aclk100", + GATE_DA(CLK_PCM0, "samsung-pcm.0", "pcm0", "aclk100", E4X12_GATE_IP_MAUDIO, 2, 0, 0, "pcm"), - GATE_DA(i2s0, "samsung-i2s.0", "i2s0", "aclk100", + GATE_DA(CLK_I2S0, "samsung-i2s.0", "i2s0", "aclk100", E4X12_GATE_IP_MAUDIO, 3, 0, 0, "iis"), - GATE(fimc_isp, "isp", "aclk200", E4X12_GATE_ISP0, 0, + GATE(CLK_FIMC_ISP, "isp", "aclk200", E4X12_GATE_ISP0, 0, CLK_IGNORE_UNUSED, 0), - GATE(fimc_drc, "drc", "aclk200", E4X12_GATE_ISP0, 1, + GATE(CLK_FIMC_DRC, "drc", "aclk200", E4X12_GATE_ISP0, 1, CLK_IGNORE_UNUSED, 0), - GATE(fimc_fd, "fd", "aclk200", E4X12_GATE_ISP0, 2, + GATE(CLK_FIMC_FD, "fd", "aclk200", E4X12_GATE_ISP0, 2, CLK_IGNORE_UNUSED, 0), - GATE(fimc_lite0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, + GATE(CLK_FIMC_LITE0, "lite0", "aclk200", E4X12_GATE_ISP0, 3, CLK_IGNORE_UNUSED, 0), - GATE(fimc_lite1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, + GATE(CLK_FIMC_LITE1, "lite1", "aclk200", E4X12_GATE_ISP0, 4, CLK_IGNORE_UNUSED, 0), - GATE(mcuisp, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, + GATE(CLK_MCUISP, "mcuisp", "aclk200", E4X12_GATE_ISP0, 5, CLK_IGNORE_UNUSED, 0), - GATE(gicisp, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, + GATE(CLK_GICISP, "gicisp", "aclk200", E4X12_GATE_ISP0, 7, CLK_IGNORE_UNUSED, 0), - GATE(smmu_isp, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, + GATE(CLK_SMMU_ISP, "smmu_isp", "aclk200", E4X12_GATE_ISP0, 8, CLK_IGNORE_UNUSED, 0), - GATE(smmu_drc, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, + GATE(CLK_SMMU_DRC, "smmu_drc", "aclk200", E4X12_GATE_ISP0, 9, CLK_IGNORE_UNUSED, 0), - GATE(smmu_fd, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, + GATE(CLK_SMMU_FD, "smmu_fd", "aclk200", E4X12_GATE_ISP0, 10, CLK_IGNORE_UNUSED, 0), - GATE(smmu_lite0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, + GATE(CLK_SMMU_LITE0, "smmu_lite0", "aclk200", E4X12_GATE_ISP0, 11, CLK_IGNORE_UNUSED, 0), - GATE(smmu_lite1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, + GATE(CLK_SMMU_LITE1, "smmu_lite1", "aclk200", E4X12_GATE_ISP0, 12, CLK_IGNORE_UNUSED, 0), - GATE(ppmuispmx, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, + GATE(CLK_PPMUISPMX, "ppmuispmx", "aclk200", E4X12_GATE_ISP0, 20, CLK_IGNORE_UNUSED, 0), - GATE(ppmuispx, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, + GATE(CLK_PPMUISPX, "ppmuispx", "aclk200", E4X12_GATE_ISP0, 21, CLK_IGNORE_UNUSED, 0), - GATE(mcuctl_isp, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, + GATE(CLK_MCUCTL_ISP, "mcuctl_isp", "aclk200", E4X12_GATE_ISP0, 23, CLK_IGNORE_UNUSED, 0), - GATE(mpwm_isp, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, + GATE(CLK_MPWM_ISP, "mpwm_isp", "aclk200", E4X12_GATE_ISP0, 24, CLK_IGNORE_UNUSED, 0), - GATE(i2c0_isp, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, + GATE(CLK_I2C0_ISP, "i2c0_isp", "aclk200", E4X12_GATE_ISP0, 25, CLK_IGNORE_UNUSED, 0), - GATE(i2c1_isp, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, + GATE(CLK_I2C1_ISP, "i2c1_isp", "aclk200", E4X12_GATE_ISP0, 26, CLK_IGNORE_UNUSED, 0), - GATE(mtcadc_isp, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, + GATE(CLK_MTCADC_ISP, "mtcadc_isp", "aclk200", E4X12_GATE_ISP0, 27, CLK_IGNORE_UNUSED, 0), - GATE(pwm_isp, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, + GATE(CLK_PWM_ISP, "pwm_isp", "aclk200", E4X12_GATE_ISP0, 28, CLK_IGNORE_UNUSED, 0), - GATE(wdt_isp, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, + GATE(CLK_WDT_ISP, "wdt_isp", "aclk200", E4X12_GATE_ISP0, 30, CLK_IGNORE_UNUSED, 0), - GATE(uart_isp, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, + GATE(CLK_UART_ISP, "uart_isp", "aclk200", E4X12_GATE_ISP0, 31, CLK_IGNORE_UNUSED, 0), - GATE(asyncaxim, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, + GATE(CLK_ASYNCAXIM, "asyncaxim", "aclk200", E4X12_GATE_ISP1, 0, CLK_IGNORE_UNUSED, 0), - GATE(smmu_ispcx, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, + GATE(CLK_SMMU_ISPCX, "smmu_ispcx", "aclk200", E4X12_GATE_ISP1, 4, CLK_IGNORE_UNUSED, 0), - GATE(spi0_isp, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, + GATE(CLK_SPI0_ISP, "spi0_isp", "aclk200", E4X12_GATE_ISP1, 12, CLK_IGNORE_UNUSED, 0), - GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, + GATE(CLK_SPI1_ISP, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13, CLK_IGNORE_UNUSED, 0), - GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), - GATE(tmu_apbif, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, 0), + GATE(CLK_G2D, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0), + GATE(CLK_TMU_APBIF, "tmu_apbif", "aclk100", E4X12_GATE_IP_PERIR, 17, 0, + 0), }; /* @@ -969,7 +924,7 @@ static void __init exynos4_clk_register_finpll(unsigned long xom) finpll_f = clk_get_rate(clk); } - fclk.id = fin_pll; + fclk.id = CLK_FIN_PLL; fclk.name = "fin_pll"; fclk.parent_name = NULL; fclk.flags = CLK_IS_ROOT; @@ -985,14 +940,14 @@ static struct of_device_id ext_clk_match[] __initdata = { }; static struct samsung_pll_clock exynos4_plls[nr_plls] __initdata = { - [apll] = PLL_A(pll_35xx, fout_apll, "fout_apll", "fin_pll", APLL_LOCK, - APLL_CON0, "fout_apll", NULL), - [mpll] = PLL_A(pll_35xx, fout_mpll, "fout_mpll", "fin_pll", + [apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", + APLL_LOCK, APLL_CON0, "fout_apll", NULL), + [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", E4X12_MPLL_LOCK, E4X12_MPLL_CON0, "fout_mpll", NULL), - [epll] = PLL_A(pll_36xx, fout_epll, "fout_epll", "fin_pll", EPLL_LOCK, - EPLL_CON0, "fout_epll", NULL), - [vpll] = PLL_A(pll_36xx, fout_vpll, "fout_vpll", "fin_pll", VPLL_LOCK, - VPLL_CON0, "fout_vpll", NULL), + [epll] = PLL_A(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", + EPLL_LOCK, EPLL_CON0, "fout_epll", NULL), + [vpll] = PLL_A(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", + VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL), }; /* register exynos4 clocks */ @@ -1009,11 +964,11 @@ static void __init exynos4_clk_init(struct device_node *np, } if (exynos4_soc == EXYNOS4210) - samsung_clk_init(np, reg_base, nr_clks, + samsung_clk_init(np, reg_base, CLK_NR_CLKS, exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), exynos4210_clk_save, ARRAY_SIZE(exynos4210_clk_save)); else - samsung_clk_init(np, reg_base, nr_clks, + samsung_clk_init(np, reg_base, CLK_NR_CLKS, exynos4_clk_regs, ARRAY_SIZE(exynos4_clk_regs), exynos4x12_clk_save, ARRAY_SIZE(exynos4x12_clk_save)); @@ -1034,10 +989,10 @@ static void __init exynos4_clk_init(struct device_node *np, vpll = samsung_clk_register_pll46xx("fout_vpll", "mout_vpllsrc", reg_base + VPLL_CON0, pll_4650c); - samsung_clk_add_lookup(apll, fout_apll); - samsung_clk_add_lookup(mpll, fout_mpll); - samsung_clk_add_lookup(epll, fout_epll); - samsung_clk_add_lookup(vpll, fout_vpll); + samsung_clk_add_lookup(apll, CLK_FOUT_APLL); + samsung_clk_add_lookup(mpll, CLK_FOUT_MPLL); + samsung_clk_add_lookup(epll, CLK_FOUT_EPLL); + samsung_clk_add_lookup(vpll, CLK_FOUT_VPLL); } else { samsung_clk_register_pll(exynos4_plls, ARRAY_SIZE(exynos4_plls), reg_base);