From patchwork Fri Sep 20 21:13:54 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 2921521 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 23B51BFF05 for ; Fri, 20 Sep 2013 21:14:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3217620459 for ; Fri, 20 Sep 2013 21:14:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 309A320462 for ; Fri, 20 Sep 2013 21:14:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754299Ab3ITVOK (ORCPT ); Fri, 20 Sep 2013 17:14:10 -0400 Received: from mail-qa0-f73.google.com ([209.85.216.73]:34331 "EHLO mail-qa0-f73.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754295Ab3ITVOH (ORCPT ); Fri, 20 Sep 2013 17:14:07 -0400 Received: by mail-qa0-f73.google.com with SMTP id cm18so14481qab.2 for ; Fri, 20 Sep 2013 14:14:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9lUBPAPrqN0aWz7Erw1MKHZEtuUHKFm+ZNHyOfa9/GQ=; b=NGjY5U7WQijHJQqdwyRihcIknrOJawVE1eel8ClpTWbL3cmKVFZ3xVelnvzNQ0hcn3 vOJs04ze1hyrKvDdSVYPxFklF3sM0J1fRUlT4RWN93B+aolczi4blVHXuHIkTSig50fr z9UtYz6Y+FvrfD9o9hebpRe/NbW95ybrVsvRpNGjC4FX3eICajgRdDQ7UN8MmeHH2Ufw R/lS7X565x0civPJcqd4llNJMZqB29X0Ud9JAeLTnjMP69ZNWifaRS0agleU11gGlb4T 9UoXSg6Wo5m941aW8ZcZNdkuPzVa3a6IAAvz3uAAm8KOmZYFN0yE7J0AALzp+xTBdgQZ XTXw== X-Gm-Message-State: ALoCoQlJaqe0xcVC9WswpTjGoRL3YqWIAyqDIhbIb5jQDCLKXONyKbO2J3r/6AUd9gIfQRNgVzdO2rM9TL7M5sp2JV/enveaEMYH+7n7oEizsCY+RM4fNqK+XSonE7UzZG00KI18J1sMWlZcCIJKSRaJdGORY8c+q/qCKyrcip1kiRRgM6q3kpXyWIvT6pzGtzdG/+VZjYlyvN7ERc4MCwGSfwdWDAvXLw== X-Received: by 10.236.54.68 with SMTP id h44mr3165862yhc.21.1379711646977; Fri, 20 Sep 2013 14:14:06 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id z45si1718860yha.7.1969.12.31.16.00.00 (version=TLSv1.1 cipher=AES128-SHA bits=128/128); Fri, 20 Sep 2013 14:14:06 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id C367731C262; Fri, 20 Sep 2013 14:14:06 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 84FA522082B; Fri, 20 Sep 2013 14:14:06 -0700 (PDT) From: Andrew Bresticker To: linux-samsung-soc@vger.kernel.org Cc: Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Kukjin Kim , Russell King , Mike Turquette , Grant Likely , Sachin Kamat , Jiri Kosina , Rahul Sharma , Leela Krishna Amudala , Stephen Boyd , Tomasz Figa , Tushar Behera , Yadwinder Singh Brar , Doug Anderson , Padmavathi Venna , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Bresticker Subject: [PATCH 3/6] clk: exynos5250: add clock ID for div_pcm0 Date: Fri, 20 Sep 2013 14:13:54 -0700 Message-Id: <1379711637-5226-3-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1379711637-5226-1-git-send-email-abrestic@chromium.org> References: <1379711637-5226-1-git-send-email-abrestic@chromium.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There is no gate for the PCM clock input to the AudioSS block, so the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that we can reference it in device trees. Signed-off-by: Andrew Bresticker Reviewed-by: Tomasz Figa --- Documentation/devicetree/bindings/clock/exynos5250-clock.txt | 1 + drivers/clk/samsung/clk-exynos5250.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt index 24765c1..67e9a47 100644 --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt +++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt @@ -62,6 +62,7 @@ clock which they consume. div_i2s1 157 div_i2s2 158 sclk_hdmiphy 159 + div_pcm0 160 [Peripheral Clock Gates] diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index adf3234..dec5376 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -108,7 +108,7 @@ enum exynos5250_clks { sclk_mmc0, sclk_mmc1, sclk_mmc2, sclk_mmc3, sclk_sata, sclk_usb3, sclk_jpeg, sclk_uart0, sclk_uart1, sclk_uart2, sclk_uart3, sclk_pwm, sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2, - div_i2s1, div_i2s2, sclk_hdmiphy, + div_i2s1, div_i2s2, sclk_hdmiphy, div_pcm0, /* gate clocks */ gscl0 = 256, gscl1, gscl2, gscl3, gscl_wa, gscl_wb, smmu_gscl0, @@ -301,7 +301,7 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { DIV(none, "div_dp", "mout_dp", DIV_DISP1_0, 24, 4), DIV(none, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4), DIV(none, "div_audio0", "mout_audio0", DIV_MAU, 0, 4), - DIV(none, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), + DIV(div_pcm0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8), DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4), DIV(none, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4), DIV(none, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),