| Message ID | 1379711637-5226-5-git-send-email-abrestic@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Andrew, On Friday 20 of September 2013 14:13:56 Andrew Bresticker wrote: > The AudioSS block on Exynos 5420 has an additional clock gate for the > ADMA bus clock. > > Signed-off-by: Andrew Bresticker <abrestic@chromium.org> > --- > Documentation/devicetree/bindings/clock/clk-exynos-audss.txt | 7 > +++++-- drivers/clk/samsung/clk-exynos-audss.c | > 8 ++++++++ include/dt-bindings/clk/exynos-audss-clk.h > | 3 ++- 3 files changed, 15 insertions(+), 3 deletions(-) [snip] > + if (of_device_is_compatible(pdev->dev.of_node, > + "samsung,exynos5420-audss-clock")) { I don't really like using such string based conditions in the code, but I guess it's just a matter of preference. I'd introduce an enum to represent supported variants and put them into the OF match table or maybe even a struct that would have a bool named has_adma_clock, true for Exynos5420 variant. Best regards, Tomasz -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index d51a2f9..a10c648 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -8,8 +8,10 @@ Required Properties: - compatible: should be one of the following: - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. - - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs. - + - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250 + SoCs. + - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420 + SoCs. - reg: physical base address and length of the controller's register set. - #clock-cells: should be 1. @@ -51,6 +53,7 @@ i2s_bus 6 sclk_i2s 7 pcm_bus 8 sclk_pcm 9 +adma 10 Exynos5420 Example 1: An example of a clock controller node using the default input clock names is listed below. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index aac5342..07c8dbd 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -145,6 +145,13 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); + if (of_device_is_compatible(pdev->dev.of_node, + "samsung,exynos5420-audss-clock")) { + clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma", + "dout_srp", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 9, 0, &lock); + } + #ifdef CONFIG_PM_SLEEP register_syscore_ops(&exynos_audss_clk_syscore_ops); #endif @@ -164,6 +171,7 @@ static int exynos_audss_clk_remove(struct platform_device *pdev) static const struct of_device_id exynos_audss_clk_of_match[] = { { .compatible = "samsung,exynos4210-audss-clock", }, { .compatible = "samsung,exynos5250-audss-clock", }, + { .compatible = "samsung,exynos5420-audss-clock", }, {}, }; diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h index 8279f42..0ae6f5a 100644 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ b/include/dt-bindings/clk/exynos-audss-clk.h @@ -19,7 +19,8 @@ #define EXYNOS_SCLK_I2S 7 #define EXYNOS_PCM_BUS 8 #define EXYNOS_SCLK_PCM 9 +#define EXYNOS_ADMA 10 -#define EXYNOS_AUDSS_MAX_CLKS 10 +#define EXYNOS_AUDSS_MAX_CLKS 11 #endif
The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> --- Documentation/devicetree/bindings/clock/clk-exynos-audss.txt | 7 +++++-- drivers/clk/samsung/clk-exynos-audss.c | 8 ++++++++ include/dt-bindings/clk/exynos-audss-clk.h | 3 ++- 3 files changed, 15 insertions(+), 3 deletions(-)