From patchwork Fri Sep 20 21:13:56 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 2921591 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 26FBB9F1E2 for ; Fri, 20 Sep 2013 21:15:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3C74420459 for ; Fri, 20 Sep 2013 21:15:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6044320457 for ; Fri, 20 Sep 2013 21:15:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754535Ab3ITVOe (ORCPT ); Fri, 20 Sep 2013 17:14:34 -0400 Received: from mail-qe0-f74.google.com ([209.85.128.74]:41314 "EHLO mail-qe0-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754302Ab3ITVOJ (ORCPT ); Fri, 20 Sep 2013 17:14:09 -0400 Received: by mail-qe0-f74.google.com with SMTP id a11so108745qen.1 for ; Fri, 20 Sep 2013 14:14:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WzrxC/iJpchO0/GayRyZJSkZi4d5m4XsQ/WaXcpIdqQ=; b=GseFcj6PQwq/K0XH13YDsnqgE6pPTS7o6DXzI3v+J8UDQiz7+WucA5bk6PsOBJyTJ6 hQfuJ49XX1+Scr+B9lfIC2xX33KzohBe6Msn0TIvSykoD+C8FDtVeRIRpYSqrDdUvyN+ +cEUy/wAi41bWkx2XqYAmGr/QU8b2s/V4dRCfeCV71m7N+OWq773/ggKTShy4m+4Z9jV lqDRiiwI4hXcl71dZ1bVaLiRefS4/4VP/86n7EHAqmkMkJyxJdwERkiN57BkwTXcgwNL MJ1Xfe5FBnYTwxEwPjBIGnaPwwqkzah0WSkx222aMTfwyDp7K5wWOldIyr1/iOO79Jpt PVtA== X-Gm-Message-State: ALoCoQkHuXzcBDE72SYjOhDdIfZDd4XnIVrnzHWVEdxO2LqmrABxCjOl4T+SubCRnN7+ICpVHOLNph7klpBDCodBD01NqbQGqwUtcmEDhUytwkfZ0CQECg0envYPk3BbhbmT9GBbs8yKafUNDZFj0pJwG0UludXa4KjsFlJVNNxX3d0kIIuSYGGnggxRVPxa96oT+sL4zMUWL2Q4tjcCeD7vfwZjqsPnlw== X-Received: by 10.236.41.100 with SMTP id g64mr3296140yhb.31.1379711648913; Fri, 20 Sep 2013 14:14:08 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id y62si1722570yha.0.1969.12.31.16.00.00 (version=TLSv1.1 cipher=AES128-SHA bits=128/128); Fri, 20 Sep 2013 14:14:08 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 90D2F31C233; Fri, 20 Sep 2013 14:14:08 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 505B222082B; Fri, 20 Sep 2013 14:14:08 -0700 (PDT) From: Andrew Bresticker To: linux-samsung-soc@vger.kernel.org Cc: Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Kukjin Kim , Russell King , Mike Turquette , Grant Likely , Sachin Kamat , Jiri Kosina , Rahul Sharma , Leela Krishna Amudala , Stephen Boyd , Tomasz Figa , Tushar Behera , Yadwinder Singh Brar , Doug Anderson , Padmavathi Venna , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Bresticker Subject: [PATCH 5/6] clk: exynos-audss: add support for Exynos 5420 Date: Fri, 20 Sep 2013 14:13:56 -0700 Message-Id: <1379711637-5226-5-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1379711637-5226-1-git-send-email-abrestic@chromium.org> References: <1379711637-5226-1-git-send-email-abrestic@chromium.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock. Signed-off-by: Andrew Bresticker --- Documentation/devicetree/bindings/clock/clk-exynos-audss.txt | 7 +++++-- drivers/clk/samsung/clk-exynos-audss.c | 8 ++++++++ include/dt-bindings/clk/exynos-audss-clk.h | 3 ++- 3 files changed, 15 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index d51a2f9..a10c648 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -8,8 +8,10 @@ Required Properties: - compatible: should be one of the following: - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. - - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs. - + - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250 + SoCs. + - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420 + SoCs. - reg: physical base address and length of the controller's register set. - #clock-cells: should be 1. @@ -51,6 +53,7 @@ i2s_bus 6 sclk_i2s 7 pcm_bus 8 sclk_pcm 9 +adma 10 Exynos5420 Example 1: An example of a clock controller node using the default input clock names is listed below. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index aac5342..07c8dbd 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -145,6 +145,13 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); + if (of_device_is_compatible(pdev->dev.of_node, + "samsung,exynos5420-audss-clock")) { + clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma", + "dout_srp", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 9, 0, &lock); + } + #ifdef CONFIG_PM_SLEEP register_syscore_ops(&exynos_audss_clk_syscore_ops); #endif @@ -164,6 +171,7 @@ static int exynos_audss_clk_remove(struct platform_device *pdev) static const struct of_device_id exynos_audss_clk_of_match[] = { { .compatible = "samsung,exynos4210-audss-clock", }, { .compatible = "samsung,exynos5250-audss-clock", }, + { .compatible = "samsung,exynos5420-audss-clock", }, {}, }; diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h index 8279f42..0ae6f5a 100644 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ b/include/dt-bindings/clk/exynos-audss-clk.h @@ -19,7 +19,8 @@ #define EXYNOS_SCLK_I2S 7 #define EXYNOS_PCM_BUS 8 #define EXYNOS_SCLK_PCM 9 +#define EXYNOS_ADMA 10 -#define EXYNOS_AUDSS_MAX_CLKS 10 +#define EXYNOS_AUDSS_MAX_CLKS 11 #endif