From patchwork Tue Sep 24 00:21:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 2931151 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CB78EBFF05 for ; Tue, 24 Sep 2013 00:22:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id E36F9201DD for ; Tue, 24 Sep 2013 00:22:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 840E3203F1 for ; Tue, 24 Sep 2013 00:21:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753898Ab3IXAVc (ORCPT ); Mon, 23 Sep 2013 20:21:32 -0400 Received: from mail-qc0-f201.google.com ([209.85.216.201]:36818 "EHLO mail-qc0-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753752Ab3IXAVY (ORCPT ); Mon, 23 Sep 2013 20:21:24 -0400 Received: by mail-qc0-f201.google.com with SMTP id u18so449410qcx.2 for ; Mon, 23 Sep 2013 17:21:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aEfwD8bYr+LuAGSoShu5bQpM2rQJPtst6h/d9lFZUWY=; b=Ll8LWm5qlmuddhPC7cP11Vrz7g4/2YpIeEdzcbJ2fBK4vpUCYHvBPlcNv1ddbdm5aM CiGiAOgEgdR+bcHtxedqPRNTN6kwq4lTMRWWYimqTMKDSE31MVDjA+agjZzBuR5LDCTx H82FrTAj8NMl+420iqeOvWpBZcY9KVcACC7jtw/2SUDj1JvNzD0oELwFEkfUuN5h+dn6 GYOVR9nRZTcCWvVTwFVT3LBJTEOlgKhyQsL9IGnT+UFz71WD/bVQktLY8F/wnWOteFRn IXEmyr48aw/48aKJ5YNwOTRmSWOBOPUBh4ifTp8osV4I0MTNlY4q36OetRvk7XjqskgS mcDQ== X-Gm-Message-State: ALoCoQnQL7BR4y4HAzr/objXRi0erLjrWn68062UuKs/AI3H4KwOAaM2Xt3ZWKMl+d3eurEyDQ4PHjRxbJXxyIPl5SDV1oSK1cNag6cywph9fcIcfAApi+LDszFR0wXlqAlTqyzD6BjHCV97WtT7igsGOE3gYxrU7UV13aZHDNbknDeLQfngqwsMXdaLlyfZuDzOK5t0yOn8OesdjWhNNaRcdfVEFUUcVg== X-Received: by 10.236.174.232 with SMTP id x68mr7609388yhl.42.1379982083345; Mon, 23 Sep 2013 17:21:23 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id a49si3958148yhc.5.1969.12.31.16.00.00 (version=TLSv1.1 cipher=AES128-SHA bits=128/128); Mon, 23 Sep 2013 17:21:23 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 169E631C1D7; Mon, 23 Sep 2013 17:21:23 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id C9BE3220A1B; Mon, 23 Sep 2013 17:21:22 -0700 (PDT) From: Andrew Bresticker To: linux-samsung-soc@vger.kernel.org, Tomasz Figa , Sylwester Nawrocki Cc: Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Kukjin Kim , Russell King , Mike Turquette , Grant Likely , Sachin Kamat , Jiri Kosina , Rahul Sharma , Leela Krishna Amudala , Stephen Boyd , Tushar Behera , Doug Anderson , Padmavathi Venna , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Bresticker Subject: [PATCH V2 2/6] clk: exynos-audss: allow input clocks to be specified in device tree Date: Mon, 23 Sep 2013 17:21:14 -0700 Message-Id: <1379982078-23381-2-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1379982078-23381-1-git-send-email-abrestic@chromium.org> References: <1379711637-5226-1-git-send-email-abrestic@chromium.org> <1379982078-23381-1-git-send-email-abrestic@chromium.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-5.8 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This allows the input clocks to the Exynos AudioSS block to be specified via device-tree bindings. Default names will be used when an input clock is not given. Signed-off-by: Andrew Bresticker --- Changes since v1: - listed input clocks as required properties --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 32 ++++++++++++++++++++-- drivers/clk/samsung/clk-exynos-audss.c | 25 +++++++++++++---- 2 files changed, 50 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 75e2e19..85b9e28 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -14,6 +14,21 @@ Required Properties: - #clock-cells: should be 1. +- clocks: + - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" + is used if not specified. + - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" + is used if not specified. + - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not + specified. + - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if + not specified. + - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not + specified. + +- clock-names: Aliases for the above clocks. They should be "pll_ref", + "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively. + The following is the list of clocks generated by the controller. Each clock is assigned an identifier and client nodes use this identifier to specify the clock which they consume. Some of the clocks are available only on a particular @@ -35,15 +50,28 @@ sclk_i2s 7 pcm_bus 8 sclk_pcm 9 -Example 1: An example of a clock controller node is listed below. +Example 1: An example of a clock controller node using the default input + clock names is listed below. + +clock_audss: audss-clock-controller@3810000 { + compatible = "samsung,exynos5250-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; +}; + +Example 2: An example of a clock controller node with the input clocks + specified. clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5250-audss-clock"; reg = <0x03810000 0x0C>; #clock-cells = <1>; + clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, + <&ext_i2s_clk>; + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk"; }; -Example 2: I2S controller node that consumes the clock generated by the clock +Example 3: I2S controller node that consumes the clock generated by the clock controller. Refer to the standard clock bindings for information about 'clocks' and 'clock-names' property. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index c512efd..afb53de 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -34,10 +34,6 @@ static unsigned long reg_save[][2] = { {ASS_CLK_GATE, 0}, }; -/* list of all parent clock list */ -static const char *mout_audss_p[] = { "fin_pll", "fout_epll" }; -static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" }; - #ifdef CONFIG_PM_SLEEP static int exynos_audss_clk_suspend(void) { @@ -66,6 +62,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = { /* register exynos_audss clocks */ static int exynos_audss_clk_probe(struct platform_device *pdev) { + const char *mout_audss_p[] = {"fin_pll", "fout_epll"}; + const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; + const char *sclk_pcm_p = "sclk_pcm0"; + struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; struct resource *res; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -88,11 +88,23 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) of_clk_add_provider(pdev->dev.of_node, of_clk_src_onecell_get, &clk_data); + pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); + pll_in = devm_clk_get(&pdev->dev, "pll_in"); + if (!IS_ERR(pll_ref)) + mout_audss_p[0] = __clk_get_name(pll_ref); + if (!IS_ERR(pll_in)) + mout_audss_p[1] = __clk_get_name(pll_in); clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss", mout_audss_p, ARRAY_SIZE(mout_audss_p), CLK_SET_RATE_NO_REPARENT, reg_base + ASS_CLK_SRC, 0, 1, 0, &lock); + cdclk = devm_clk_get(&pdev->dev, "cdclk"); + sclk_audio = devm_clk_get(&pdev->dev, "sclk_audio"); + if (!IS_ERR(cdclk)) + mout_i2s_p[1] = __clk_get_name(cdclk); + if (!IS_ERR(sclk_audio)) + mout_i2s_p[2] = __clk_get_name(sclk_audio); clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s", mout_i2s_p, ARRAY_SIZE(mout_i2s_p), CLK_SET_RATE_NO_REPARENT, @@ -126,8 +138,11 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) "sclk_pcm", CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 4, 0, &lock); + sclk_pcm_in = devm_clk_get(&pdev->dev, "sclk_pcm_in"); + if (!IS_ERR(sclk_pcm_in)) + sclk_pcm_p = __clk_get_name(sclk_pcm_in); clk_table[EXYNOS_SCLK_PCM] = clk_register_gate(NULL, "sclk_pcm", - "div_pcm0", CLK_SET_RATE_PARENT, + sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); #ifdef CONFIG_PM_SLEEP