From patchwork Tue Sep 24 00:21:17 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 2931201 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 17AFD9F289 for ; Tue, 24 Sep 2013 00:22:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2FA3A201F6 for ; Tue, 24 Sep 2013 00:22:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 41278201DD for ; Tue, 24 Sep 2013 00:22:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753948Ab3IXAWS (ORCPT ); Mon, 23 Sep 2013 20:22:18 -0400 Received: from mail-ve0-f201.google.com ([209.85.128.201]:40514 "EHLO mail-ve0-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753783Ab3IXAV0 (ORCPT ); Mon, 23 Sep 2013 20:21:26 -0400 Received: by mail-ve0-f201.google.com with SMTP id c14so448720vea.4 for ; Mon, 23 Sep 2013 17:21:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=J3Smpama8FQGJehYs3/ElQWROHVd7RVkg4t/VTd2SlQ=; b=Qsw6PaQbwzIzucGtb+ZI6eWzlEOipd0ld06W9BRLdfWsQY8BaObQYJj9l0HAbWgEcR mHYdEnDF/QojP+Tikbv60CFzmAHCEJF3qahPpEHs/12kqoV2mnqXKJM4rry03d47Jw++ yb7Oetr9/rWL3WAjfkzDur+hS9M8hI9IlNr3z4fOtQXrcFKysjNYSrAkQ1xJ3Vv6UfTk smAX8TuxR0sRe+v0rs+WP4I2RMQsh0WgNoJKmfLOjHrkEJn7cTUGO2JeD/Rtew4UB0UG 0tcn8c+chfPjJts/UDrTGqAI3lmuinHf17TKFd4AD42/5ZQ/WGy8x+PifPbNcZZSGe2x GM7Q== X-Gm-Message-State: ALoCoQkrrdPsAEkbb/PrydFOrd2S/f6N6VCnNm10c14BuC3O7QHrz+2WpMz1z8z0IksnwE8Q7/LCDF2KXJ33IBiWpqIESLRaSUUgq53wlR1Af0mu88v+g7H6+7Eto96cgQtG5RYct9lZLFs0uUutnSS5YKwUyQJYL/10DiQVlvyIFfToM2WtLarCnOeNmL7uHszYnUAXyqKINnr7GD8z42mEDTS3/+IquA== X-Received: by 10.236.209.103 with SMTP id r67mr9215145yho.35.1379982085884; Mon, 23 Sep 2013 17:21:25 -0700 (PDT) Received: from corp2gmr1-2.hot.corp.google.com (corp2gmr1-2.hot.corp.google.com [172.24.189.93]) by gmr-mx.google.com with ESMTPS id z45si3957110yha.7.1969.12.31.16.00.00 (version=TLSv1.1 cipher=AES128-SHA bits=128/128); Mon, 23 Sep 2013 17:21:25 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-2.hot.corp.google.com (Postfix) with ESMTP id 9F1D25A4278; Mon, 23 Sep 2013 17:21:25 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 5E568220A1B; Mon, 23 Sep 2013 17:21:25 -0700 (PDT) From: Andrew Bresticker To: linux-samsung-soc@vger.kernel.org, Tomasz Figa , Sylwester Nawrocki Cc: Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Kukjin Kim , Russell King , Mike Turquette , Grant Likely , Sachin Kamat , Jiri Kosina , Rahul Sharma , Leela Krishna Amudala , Stephen Boyd , Tushar Behera , Doug Anderson , Padmavathi Venna , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Bresticker Subject: [PATCH V2 5/6] clk: exynos-audss: add support for Exynos 5420 Date: Mon, 23 Sep 2013 17:21:17 -0700 Message-Id: <1379982078-23381-5-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1379982078-23381-1-git-send-email-abrestic@chromium.org> References: <1379711637-5226-1-git-send-email-abrestic@chromium.org> <1379982078-23381-1-git-send-email-abrestic@chromium.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-5.8 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock. Signed-off-by: Andrew Bresticker --- Changes since v1: - added type enum and made comparison against that instead of compatibility string --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 7 +++-- drivers/clk/samsung/clk-exynos-audss.c | 35 ++++++++++++++++++---- include/dt-bindings/clk/exynos-audss-clk.h | 3 +- 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 85b9e28..180e883 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -8,8 +8,10 @@ Required Properties: - compatible: should be one of the following: - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. - - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs. - + - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250 + SoCs. + - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420 + SoCs. - reg: physical base address and length of the controller's register set. - #clock-cells: should be 1. @@ -49,6 +51,7 @@ i2s_bus 6 sclk_i2s 7 pcm_bus 8 sclk_pcm 9 +adma 10 Exynos5420 Example 1: An example of a clock controller node using the default input clock names is listed below. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index afb53de..8ccf3788 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -19,6 +19,12 @@ #include +enum exynos_audss_clk_type { + TYPE_EXYNOS4210, + TYPE_EXYNOS5250, + TYPE_EXYNOS5420, +}; + static DEFINE_SPINLOCK(lock); static struct clk **clk_table; static void __iomem *reg_base; @@ -59,6 +65,16 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = { }; #endif /* CONFIG_PM_SLEEP */ +static const struct of_device_id exynos_audss_clk_of_match[] = { + { .compatible = "samsung,exynos4210-audss-clock", + .data = (void *)TYPE_EXYNOS4210, }, + { .compatible = "samsung,exynos5250-audss-clock", + .data = (void *)TYPE_EXYNOS5250, }, + { .compatible = "samsung,exynos5420-audss-clock", + .data = (void *)TYPE_EXYNOS5420, }, + {}, +}; + /* register exynos_audss clocks */ static int exynos_audss_clk_probe(struct platform_device *pdev) { @@ -67,6 +83,13 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) const char *sclk_pcm_p = "sclk_pcm0"; struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; struct resource *res; + const struct of_device_id *match; + enum exynos_audss_clk_type variant; + + match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node); + if (!match) + return -EINVAL; + variant = (enum exynos_audss_clk_type)match->data; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg_base = devm_ioremap_resource(&pdev->dev, res); @@ -145,6 +168,12 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); + if (variant == TYPE_EXYNOS5420) { + clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma", + "dout_srp", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 9, 0, &lock); + } + #ifdef CONFIG_PM_SLEEP register_syscore_ops(&exynos_audss_clk_syscore_ops); #endif @@ -168,12 +197,6 @@ static int exynos_audss_clk_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id exynos_audss_clk_of_match[] = { - { .compatible = "samsung,exynos4210-audss-clock", }, - { .compatible = "samsung,exynos5250-audss-clock", }, - {}, -}; - static struct platform_driver exynos_audss_clk_driver = { .driver = { .name = "exynos-audss-clk", diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h index 8279f42..0ae6f5a 100644 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ b/include/dt-bindings/clk/exynos-audss-clk.h @@ -19,7 +19,8 @@ #define EXYNOS_SCLK_I2S 7 #define EXYNOS_PCM_BUS 8 #define EXYNOS_SCLK_PCM 9 +#define EXYNOS_ADMA 10 -#define EXYNOS_AUDSS_MAX_CLKS 10 +#define EXYNOS_AUDSS_MAX_CLKS 11 #endif