From patchwork Wed Sep 25 21:12:51 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 2944611 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CA4DE9F289 for ; Wed, 25 Sep 2013 21:21:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C1F1420158 for ; Wed, 25 Sep 2013 21:21:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B73F92010A for ; Wed, 25 Sep 2013 21:21:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755091Ab3IYVVI (ORCPT ); Wed, 25 Sep 2013 17:21:08 -0400 Received: from mail-qc0-f201.google.com ([209.85.216.201]:59840 "EHLO mail-qc0-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755033Ab3IYVVH (ORCPT ); Wed, 25 Sep 2013 17:21:07 -0400 Received: by mail-qc0-f201.google.com with SMTP id u18so36576qcx.0 for ; Wed, 25 Sep 2013 14:21:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V3fjAtw7p6w5iKxeQVvYqugjfqy/ruvA7WKijYaFeBM=; b=KLj2n6IgIebDJu4kncIVJz5u+lm6Bt7Egu/8JoBr2eI6krmoONtYbuFo23zxefqHOz 1stZSP3wahoeQpDcE5tCV4DXF2JCJpH7wMm0A+5jQSYg8FBfXBR777tNZPRhAZMGx+1p to/F4saTgQN8lyWYJ7TA4LCpxhN+GXEdxXF5S9SZOa5ki5iVtm9nTFSCxd8nyf7dLXpo tO/pk1CwpF9UKPeiPhIABuB0iyTshFB/2mel1ghsMeotH+JBWE7Zco84MZnJTZoZ18sV QawGc3MmaPkdSpnLGcDGZs0xqX4JJwLnH+uXH059RLrv5ObOqrHbJVD9Hc6iXmd910/U RHWw== X-Gm-Message-State: ALoCoQlKP6/WH/soqOB3g23OMfh8hXHOHdHwOp+3p53uyEefyyMYI0YW1nKqDnY7ubDvWnd2E9Mpiwfe3kQ286gA5Ef/e7X+4dnru5T1y2U3QFlrbSfAnOPbvc+L4O1ZXssMNX3R0sH42AhxuvEOj8wVRcBPpvdhtrbEbK971Py7TcALP2gWDICQ2Of8W8OdO4dd86lANk461t8IOjCh0APPDFjaY6BADA== X-Received: by 10.236.186.101 with SMTP id v65mr10155881yhm.12.1380143577705; Wed, 25 Sep 2013 14:12:57 -0700 (PDT) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id s21si6099017yhc.1.1969.12.31.16.00.00 (version=TLSv1.1 cipher=AES128-SHA bits=128/128); Wed, 25 Sep 2013 14:12:57 -0700 (PDT) Received: from abrestic.mtv.corp.google.com (abrestic.mtv.corp.google.com [172.22.72.111]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id 6CB2131C1DA; Wed, 25 Sep 2013 14:12:57 -0700 (PDT) Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id 2C85C220862; Wed, 25 Sep 2013 14:12:57 -0700 (PDT) From: Andrew Bresticker To: Tomasz Figa , Sylwester Nawrocki , linux-samsung-soc@vger.kernel.org, Stephen Boyd Cc: Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Kukjin Kim , Russell King , Mike Turquette , Grant Likely , Sachin Kamat , Jiri Kosina , Rahul Sharma , Leela Krishna Amudala , Tushar Behera , Doug Anderson , Padmavathi Venna , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Bresticker Subject: [PATCH V4 5/6] clk: exynos-audss: add support for Exynos 5420 Date: Wed, 25 Sep 2013 14:12:51 -0700 Message-Id: <1380143572-11741-5-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1380143572-11741-1-git-send-email-abrestic@chromium.org> References: <1380046016-5811-1-git-send-email-abrestic@chromium.org> <1380143572-11741-1-git-send-email-abrestic@chromium.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The AudioSS block on Exynos 5420 has an additional clock gate for the ADMA bus clock. Signed-off-by: Andrew Bresticker --- Changes since v3: - set clk_data.clk_num to correct value in non-5420 case Changes since v1: - added type enum and made comparison against that instead of compatibility string --- .../devicetree/bindings/clock/clk-exynos-audss.txt | 7 ++-- drivers/clk/samsung/clk-exynos-audss.c | 40 ++++++++++++++++++---- include/dt-bindings/clk/exynos-audss-clk.h | 3 +- 3 files changed, 40 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt index 85b9e28..180e883 100644 --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt +++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt @@ -8,8 +8,10 @@ Required Properties: - compatible: should be one of the following: - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs. - - "samsung,exynos5250-audss-clock" - controller compatible with all Exynos5 SoCs. - + - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250 + SoCs. + - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420 + SoCs. - reg: physical base address and length of the controller's register set. - #clock-cells: should be 1. @@ -49,6 +51,7 @@ i2s_bus 6 sclk_i2s 7 pcm_bus 8 sclk_pcm 9 +adma 10 Exynos5420 Example 1: An example of a clock controller node using the default input clock names is listed below. diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c index 7cb10f2..e607176 100644 --- a/drivers/clk/samsung/clk-exynos-audss.c +++ b/drivers/clk/samsung/clk-exynos-audss.c @@ -19,6 +19,12 @@ #include +enum exynos_audss_clk_type { + TYPE_EXYNOS4210, + TYPE_EXYNOS5250, + TYPE_EXYNOS5420, +}; + static DEFINE_SPINLOCK(lock); static struct clk **clk_table; static void __iomem *reg_base; @@ -59,6 +65,16 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = { }; #endif /* CONFIG_PM_SLEEP */ +static const struct of_device_id exynos_audss_clk_of_match[] = { + { .compatible = "samsung,exynos4210-audss-clock", + .data = (void *)TYPE_EXYNOS4210, }, + { .compatible = "samsung,exynos5250-audss-clock", + .data = (void *)TYPE_EXYNOS5250, }, + { .compatible = "samsung,exynos5420-audss-clock", + .data = (void *)TYPE_EXYNOS5420, }, + {}, +}; + /* register exynos_audss clocks */ static int exynos_audss_clk_probe(struct platform_device *pdev) { @@ -68,6 +84,13 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"}; const char *sclk_pcm_p = "sclk_pcm0"; struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; + const struct of_device_id *match; + enum exynos_audss_clk_type variant; + + match = of_match_node(exynos_audss_clk_of_match, pdev->dev.of_node); + if (!match) + return -EINVAL; + variant = (enum exynos_audss_clk_type)match->data; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); reg_base = devm_ioremap_resource(&pdev->dev, res); @@ -83,7 +106,10 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) return -ENOMEM; clk_data.clks = clk_table; - clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; + if (variant == TYPE_EXYNOS5420) + clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS; + else + clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS - 1; pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); pll_in = devm_clk_get(&pdev->dev, "pll_in"); @@ -142,6 +168,12 @@ static int exynos_audss_clk_probe(struct platform_device *pdev) sclk_pcm_p, CLK_SET_RATE_PARENT, reg_base + ASS_CLK_GATE, 5, 0, &lock); + if (variant == TYPE_EXYNOS5420) { + clk_table[EXYNOS_ADMA] = clk_register_gate(NULL, "adma", + "dout_srp", CLK_SET_RATE_PARENT, + reg_base + ASS_CLK_GATE, 9, 0, &lock); + } + for (i = 0; i < clk_data.clk_num; i++) { if (IS_ERR(clk_table[i])) { dev_err(&pdev->dev, "failed to register clock %d\n", i); @@ -188,12 +220,6 @@ static int exynos_audss_clk_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id exynos_audss_clk_of_match[] = { - { .compatible = "samsung,exynos4210-audss-clock", }, - { .compatible = "samsung,exynos5250-audss-clock", }, - {}, -}; - static struct platform_driver exynos_audss_clk_driver = { .driver = { .name = "exynos-audss-clk", diff --git a/include/dt-bindings/clk/exynos-audss-clk.h b/include/dt-bindings/clk/exynos-audss-clk.h index 8279f42..0ae6f5a 100644 --- a/include/dt-bindings/clk/exynos-audss-clk.h +++ b/include/dt-bindings/clk/exynos-audss-clk.h @@ -19,7 +19,8 @@ #define EXYNOS_SCLK_I2S 7 #define EXYNOS_PCM_BUS 8 #define EXYNOS_SCLK_PCM 9 +#define EXYNOS_ADMA 10 -#define EXYNOS_AUDSS_MAX_CLKS 10 +#define EXYNOS_AUDSS_MAX_CLKS 11 #endif