From patchwork Thu Dec 5 18:15:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 3290561 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D6C4E9F388 for ; Thu, 5 Dec 2013 18:16:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 908C720531 for ; Thu, 5 Dec 2013 18:16:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 569052052F for ; Thu, 5 Dec 2013 18:16:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757586Ab3LESQx (ORCPT ); Thu, 5 Dec 2013 13:16:53 -0500 Received: from mail-qc0-f202.google.com ([209.85.216.202]:49855 "EHLO mail-qc0-f202.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757553Ab3LESQd (ORCPT ); Thu, 5 Dec 2013 13:16:33 -0500 Received: by mail-qc0-f202.google.com with SMTP id i17so635763qcy.3 for ; Thu, 05 Dec 2013 10:16:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FirOTy+AgJakBpoY3S8l81N9SeACuMYwjoWCQf/a7W0=; b=g4BKU3oxUO8QteTRe7AIUbU8tC4yolqs5jhCF14LsFpQ5QSUdGghNLMooWpW8n+Gwt Wlw+lZReYfdvlXOjvhmhJhO0r4vbe6xeUcPBaVXFF0KtRkL0FN3+EKa2vTlPP1XEJ/IS xe8FwXvLC5heRVXPR/ZSobeEhKPR+Lx79i9B8emr3qI1+gSl6DT/v80QIBXx6YWoCB50 ERbgUvfoNflgI6uglRhr/7NVDjJkMNBaW/6zTXZpo/ss0DT3cRXLZirklnCAl33H9QX9 i3KhvWH4Rg1bBw/wJxC4GWjrZ7+MniwN53PP1q7aUZbNQ+5r/raohSMafImN1ktaGKwr /Xxg== X-Gm-Message-State: ALoCoQlxlH7JJY788ZWSmPadOJtJzwnw16gSgzT1LKLQd7bQ61ifK8WHBUxs3aDTIE/SekJmwiLt79XWm5LAzXtqqXIg4uZOO++Y5y/ca5c9aH68KmtpNEF+y1hBGSY7v+shkLb6nmX8DX6ekUq5oPrIM83V2Hk5QU1drdyOD658djKjv0TmRCXurHZ386yz94J3gh8MwHEqskSsILTMp4Eo8VLsSCNEpA== X-Received: by 10.59.5.68 with SMTP id ck4mr29994178ved.9.1386267392112; Thu, 05 Dec 2013 10:16:32 -0800 (PST) Received: from corp2gmr1-1.hot.corp.google.com (corp2gmr1-1.hot.corp.google.com [172.24.189.92]) by gmr-mx.google.com with ESMTPS id o30si6636695yhn.1.2013.12.05.10.16.32 for (version=TLSv1.1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 05 Dec 2013 10:16:32 -0800 (PST) Received: from tictac.mtv.corp.google.com (tictac.mtv.corp.google.com [172.22.72.141]) by corp2gmr1-1.hot.corp.google.com (Postfix) with ESMTP id DAC4831C22B; Thu, 5 Dec 2013 10:16:31 -0800 (PST) Received: by tictac.mtv.corp.google.com (Postfix, from userid 121310) id 89D618080F; Thu, 5 Dec 2013 10:16:31 -0800 (PST) From: Doug Anderson To: Wim Van Sebroeck , Guenter Roeck Cc: Leela Krishna Amudala , Olof Johansson , Tomasz Figa , Kukjin Kim , Doug Anderson , Ben Dooks , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] watchdog: s3c2410_wdt: Report when the watchdog reset the system Date: Thu, 5 Dec 2013 10:15:29 -0800 Message-Id: <1386267329-9941-2-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 1.8.5.1 In-Reply-To: <1386267329-9941-1-git-send-email-dianders@chromium.org> References: <1386008082-28740-1-git-send-email-dianders@chromium.org> <1386267329-9941-1-git-send-email-dianders@chromium.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP A good watchdog driver is supposed to report when it was responsible for resetting the system. Implement this for the s3c2410, at least on exynos5250 and exynos5420 where we already have a pointer to the PMU registers to read the information. Note that exynos4 SoCs also provide the reset status, but providing that is left as an exercise for future changes and is not plumbed up in this patch series. Also note the exynos4 SoCs don't appear to need any PMU config, which is why this patch separates the concepts of having PMU Registers vs. needing PMU Config. Signed-off-by: Doug Anderson --- Changes in v2: - Explained QUIRK organization in patch descritpion. - Reduced indentation as per Olof and Tomasz suggestion. - Now atop proposed v12 of Leela Krishna's patches. - NEEDS => HAS, EXYNOS5 prefix drivers/watchdog/s3c2410_wdt.c | 42 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 6a00299..45a9503 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -62,9 +62,15 @@ #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) +#define EXYNOS5_RST_STAT_REG_OFFSET 0x0404 #define EXYNOS5_WDT_DISABLE_REG_OFFSET 0x0408 #define EXYNOS5_WDT_MASK_RESET_REG_OFFSET 0x040c #define QUIRK_HAS_PMU_CONFIG (1 << 0) +#define QUIRK_HAS_RST_STAT (1 << 1) + +/* These quirks require that we have a PMU register map */ +#define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \ + QUIRK_HAS_RST_STAT) static bool nowayout = WATCHDOG_NOWAYOUT; static int tmr_margin; @@ -98,6 +104,9 @@ MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug (default 0)"); * timer reset functionality. * @mask_bit: Bit number for the watchdog timer in the disable register and the * mask reset register. + * @rst_stat_reg: Offset in pmureg for the register that has the reset status. + * @rst_stat_bit: Bit number in the rst_stat register indicating a watchdog + * reset. * @quirks: A bitfield of quirks. */ @@ -105,6 +114,8 @@ struct s3c2410_wdt_variant { int disable_reg; int mask_reset_reg; int mask_bit; + int rst_stat_reg; + int rst_stat_bit; u32 quirks; }; @@ -131,14 +142,20 @@ static const struct s3c2410_wdt_variant drv_data_exynos5250 = { .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, .mask_bit = 20, - .quirks = QUIRK_HAS_PMU_CONFIG + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, + .rst_stat_bit = 20, + .quirks = QUIRK_HAS_PMU_CONFIG | + QUIRK_HAS_RST_STAT, }; static const struct s3c2410_wdt_variant drv_data_exynos5420 = { .disable_reg = EXYNOS5_WDT_DISABLE_REG_OFFSET, .mask_reset_reg = EXYNOS5_WDT_MASK_RESET_REG_OFFSET, .mask_bit = 0, - .quirks = QUIRK_HAS_PMU_CONFIG + .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET, + .rst_stat_bit = 9, + .quirks = QUIRK_HAS_PMU_CONFIG | + QUIRK_HAS_RST_STAT, }; static const struct of_device_id s3c2410_wdt_match[] = { @@ -427,6 +444,23 @@ static inline void s3c2410wdt_cpufreq_deregister(struct s3c2410_wdt *wdt) } #endif +static inline unsigned int s3c2410wdt_get_bootstatus(struct s3c2410_wdt *wdt) +{ + unsigned int rst_stat; + int ret; + + if (!(wdt->drv_data->quirks & QUIRK_HAS_RST_STAT)) + return 0; + + ret = regmap_read(wdt->pmureg, wdt->drv_data->rst_stat_reg, &rst_stat); + if (ret) + dev_warn(wdt->dev, "Couldn't get RST_STAT register\n"); + else if (rst_stat & BIT(wdt->drv_data->rst_stat_bit)) + return WDIOF_CARDRESET; + + return 0; +} + /* s3c2410_get_wdt_driver_data */ static inline struct s3c2410_wdt_variant * get_wdt_drv_data(struct platform_device *pdev) @@ -464,7 +498,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev) wdt->wdt_device = s3c2410_wdd; wdt->drv_data = get_wdt_drv_data(pdev); - if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG) { + if (wdt->drv_data->quirks & QUIRKS_HAVE_PMUREG) { wdt->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node, "samsung,syscon-phandle"); if (IS_ERR(wdt->pmureg)) { @@ -535,6 +569,8 @@ static int s3c2410wdt_probe(struct platform_device *pdev) watchdog_set_nowayout(&wdt->wdt_device, nowayout); + wdt->wdt_device.bootstatus = s3c2410wdt_get_bootstatus(wdt); + ret = watchdog_register_device(&wdt->wdt_device); if (ret) { dev_err(dev, "cannot register watchdog (%d)\n", ret);