From patchwork Tue Dec 10 10:55:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vivek Gautam X-Patchwork-Id: 3317321 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DD0E3C0D4A for ; Tue, 10 Dec 2013 10:57:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B674E20221 for ; Tue, 10 Dec 2013 10:57:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7D4BA20220 for ; Tue, 10 Dec 2013 10:57:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752774Ab3LJK45 (ORCPT ); Tue, 10 Dec 2013 05:56:57 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:64330 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752413Ab3LJK4L (ORCPT ); Tue, 10 Dec 2013 05:56:11 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MXL00J7E7PF6070@mailout2.samsung.com>; Tue, 10 Dec 2013 19:56:03 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.123]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id B4.E0.15387.343F6A25; Tue, 10 Dec 2013 19:56:03 +0900 (KST) X-AuditID: cbfee68f-b7f256d000003c1b-7e-52a6f3435f8e Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id A6.D6.15903.343F6A25; Tue, 10 Dec 2013 19:56:03 +0900 (KST) Received: from vivekkumarg-linuxpc.sisodomain.com ([107.108.214.169]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MXL00FRH7P6F400@mmp2.samsung.com>; Tue, 10 Dec 2013 19:56:03 +0900 (KST) From: Vivek Gautam To: linux-usb@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org, gregkh@linuxfoundation.org, balbi@ti.com, sarah.a.sharp@linux.intel.com, kgene.kim@samsung.com, kishon@ti.com, jg1.han@samsung.com, jwerner@chromium.org Subject: [PATCH RFC 2/4] xhci: Add quirk for DWC3-Exynos controller Date: Tue, 10 Dec 2013 16:25:24 +0530 Message-id: <1386672926-26885-3-git-send-email-gautam.vivek@samsung.com> X-Mailer: git-send-email 1.7.6.5 In-reply-to: <1386672926-26885-1-git-send-email-gautam.vivek@samsung.com> References: <1386672926-26885-1-git-send-email-gautam.vivek@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjkeLIzCtJLcpLzFFi42JZI2JSrev8eVmQwbyj+hYH79dbNC9ez2Zx eeElVouOQ4+ZLHoXXGWzuPC0Byi2aw6bxewl/SwWM87vY7JYtKyV2aL5xClmB26P2Q0XWTzm nQz02D93DbtH35ZVjB7Hb2xn8vi8SS6ALYrLJiU1J7MstUjfLoEr4/76l0wF+wUrttw/xtLA OJGvi5GTQ0LAROJrQxcThC0mceHeejYQW0hgKaPE6iZBmJqPj5qB4lxA8emMEj1ft7JAOFOY JBa/uc4OUsUmoCvR9HYXI4gtIuAgsWTpHbAOZoFbjBItUztYQRLCAs4Sa/vXg9ksAqoSndPe gq3jFfCQ+Px/PhvEOgWJN7efMYPYnAKeEsu7DrBCnOQh0XX/PjPIUAmBXewSn97NZoEYJCDx bfIhIJsDKCErsekAM8QcSYmDK26wTGAUXsDIsIpRNLUguaA4Kb3IWK84Mbe4NC9dLzk/dxMj MC5O/3vWv4Px7gHrQ4zJQOMmMkuJJucD4yqvJN7Q2MzIwtTE1NjI3NKMNGElcd77D5OChATS E0tSs1NTC1KL4otKc1KLDzEycXBKNTA2arR93faIPXnzb/eKr17Lyo63FNUeC+VN3Pz93ber l/Vq5J2u5X/jC9qhcqPo3tqiM2o90Ze5g7l1z2dLS4faLw2c1il/P/1UoZdIelyH123foCXz F1/vM/94LeR16dotc7851jaKfFihnBZ54WfU6zMH5thLvXp8Xn7u2S1RbyRs3MwYWLyVWIoz Eg21mIuKEwF2cq3+oQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDIsWRmVeSWpSXmKPExsVy+t9jQV3nz8uCDHbtV7M4eL/eonnxejaL ywsvsVp0HHrMZNG74CqbxYWnPUCxXXPYLGYv6WexmHF+H5PFomWtzBbNJ04xO3B7zG64yOIx 72Sgx/65a9g9+rasYvQ4fmM7k8fnTXIBbFENjDYZqYkpqUUKqXnJ+SmZeem2St7B8c7xpmYG hrqGlhbmSgp5ibmptkouPgG6bpk5QOcpKZQl5pQChQISi4uV9O0wTQgNcdO1gGmM0PUNCYLr MTJAAwlrGDPur3/JVLBfsGLL/WMsDYwT+boYOTkkBEwkPj5qZoOwxSQu3FsPZHNxCAlMZ5To +bqVBcKZwiSx+M11dpAqNgFdiaa3uxhBbBEBB4klS++AdTAL3GKUaJnawQqSEBZwlljbvx7M ZhFQleic9hZsBa+Ah8Tn//Oh1ilIvLn9jBnE5hTwlFjedQCsXgiopuv+feYJjLwLGBlWMYqm FiQXFCel5xrpFSfmFpfmpesl5+duYgTH3TPpHYyrGiwOMQpwMCrx8Er8WxokxJpYVlyZe4hR goNZSYR324tlQUK8KYmVValF+fFFpTmpxYcYk4GumsgsJZqcD0wJeSXxhsYm5qbGppYmFiZm lqQJK4nzHmy1DhQSSE8sSc1OTS1ILYLZwsTBKdXAGFA1iWNXqsm+Zbpq5xf1Sp9YofYmNMFz bRmr4MQ36v8ko1r/vb50UThMptHNoPZj9psNq8r+Fs6arhLtxifItSDlgXqn4qTWelHLNq7Z Zpa9D/sZP6YXTY/+N/VWxVnfdZoX3CdUnY0OXzIn8LX342uf3ZskdJSKT/k9YJnX/HwV05k9 LslPlFiKMxINtZiLihMBq9WV3f8CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DWC3-exynos eXtensible host controller on Exynos5420 SoC is quirky in a way that the PHY needs to be tuned to get it working at SuperSpeed. By default this PHY works as High-speed phy and therefore detects even Super-speed devices as high-speed ones. So, the PHY needs to be tuned after controller has been reset. Adding a xHCI quirk for this purpose. Signed-off-by: Vivek Gautam --- drivers/usb/host/xhci-plat.c | 19 +++++++++++++++++++ drivers/usb/host/xhci.h | 1 + 2 files changed, 20 insertions(+), 0 deletions(-) diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c index d9c169f..395c9e9 100644 --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c @@ -21,6 +21,25 @@ static void xhci_plat_quirks(struct device *dev, struct xhci_hcd *xhci) { + struct device *parent_dev; + struct device *vendor_parent_dev; + + parent_dev = dev->parent; + vendor_parent_dev = parent_dev->parent; + + /* + * The DWC3-exynos host controller on Exynos5420 SoC is quirky + * in a way that the PHY needs to be tuned to get it working + * at SuperSpeed. By default this PHY works as High-speed phy + * and so detects even Super-speed devices as high-speed ones. + * Therefor the PHY needs to be tuned after controller + * has been reset, since a controller reset actually forces the + * PHY to fall back to its default state wherein it works as + * High-Speed PHY only. + */ + if (!strstr(dev_name(vendor_parent_dev), "exynos")) + xhci->quirks |= XHCI_DWC3_EXYNOS; + /* * As of now platform drivers don't provide MSI support so we ensure * here that the generic code does not try to make a pci_dev from our diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h index 7807f62..f69af8c 100644 --- a/drivers/usb/host/xhci.h +++ b/drivers/usb/host/xhci.h @@ -1560,6 +1560,7 @@ struct xhci_hcd { #define XHCI_PLAT (1 << 16) #define XHCI_SLOW_SUSPEND (1 << 17) #define XHCI_SPURIOUS_WAKEUP (1 << 18) +#define XHCI_DWC3_EXYNOS (1 << 19) unsigned int num_active_eps; unsigned int limit_active_eps; /* There are two roothubs to keep track of bus suspend info for */