diff --git a/drivers/phy/phy-exynos4212-usb2.c b/drivers/phy/phy-exynos4212-usb2.c
new file mode 100644
index 0000000..8f7578a
--- /dev/null
+++ b/drivers/phy/phy-exynos4212-usb2.c
@@ -0,0 +1,452 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4210 and 4212 support
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski <k.debski@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include "phy-samsung-usb2.h"
+
+/* Exynos USB PHY registers */
+
+/* PHY power control */
+#define EXYNOS_421x_UPHYPWR			0x0
+
+#define EXYNOS_421x_UPHYPWR_PHY0_SUSPEND	BIT(0)
+#define EXYNOS_421x_UPHYPWR_PHY0_PWR		BIT(3)
+#define EXYNOS_421x_UPHYPWR_PHY0_OTG_PWR	BIT(4)
+#define EXYNOS_421x_UPHYPWR_PHY0_SLEEP		BIT(5)
+#define EXYNOS_421x_UPHYPWR_PHY0 ( \
+	EXYNOS_421x_UPHYPWR_PHY0_SUSPEND | \
+	EXYNOS_421x_UPHYPWR_PHY0_PWR | \
+	EXYNOS_421x_UPHYPWR_PHY0_OTG_PWR | \
+	EXYNOS_421x_UPHYPWR_PHY0_SLEEP)
+
+#define EXYNOS_421x_UPHYPWR_PHY1_SUSPEND	BIT(6)
+#define EXYNOS_421x_UPHYPWR_PHY1_PWR		BIT(7)
+#define EXYNOS_421x_UPHYPWR_PHY1_SLEEP		BIT(8)
+#define EXYNOS_421x_UPHYPWR_PHY1 ( \
+	EXYNOS_421x_UPHYPWR_PHY1_SUSPEND | \
+	EXYNOS_421x_UPHYPWR_PHY1_PWR | \
+	EXYNOS_421x_UPHYPWR_PHY1_SLEEP)
+
+#define EXYNOS_4210_UPHYPWR_HSCI0_SUSPEND	BIT(9)
+#define EXYNOS_4210_UPHYPWR_HSCI0_SLEEP		BIT(10)
+#define EXYNOS_4210_UPHYPWR_HSCI0 ( \
+	EXYNOS_4210_UPHYPWR_HSCI0_SUSPEND | \
+	EXYNOS_4210_UPHYPWR_HSCI0_SLEEP)
+
+#define EXYNOS_4210_UPHYPWR_HSCI1_SUSPEND	BIT(11)
+#define EXYNOS_4210_UPHYPWR_HSCI1_SLEEP		BIT(12)
+#define EXYNOS_4210_UPHYPWR_HSCI1 ( \
+	EXYNOS_4210_UPHYPWR_HSCI1_SUSPEND | \
+	EXYNOS_4210_UPHYPWR_HSCI1_SLEEP)
+
+#define EXYNOS_4212_UPHYPWR_HSCI0_SUSPEND	BIT(9)
+#define EXYNOS_4212_UPHYPWR_HSCI0_PWR		BIT(10)
+#define EXYNOS_4212_UPHYPWR_HSCI0_SLEEP		BIT(11)
+#define EXYNOS_4212_UPHYPWR_HSCI0 ( \
+	EXYNOS_4212_UPHYPWR_HSCI0_SUSPEND | \
+	EXYNOS_4212_UPHYPWR_HSCI0_PWR | \
+	EXYNOS_4212_UPHYPWR_HSCI0_SLEEP)
+
+#define EXYNOS_4212_UPHYPWR_HSCI1_SUSPEND	BIT(12)
+#define EXYNOS_4212_UPHYPWR_HSCI1_PWR		BIT(13)
+#define EXYNOS_4212_UPHYPWR_HSCI1_SLEEP		BIT(14)
+#define EXYNOS_4212_UPHYPWR_HSCI1 ( \
+	EXYNOS_4212_UPHYPWR_HSCI1_SUSPEND | \
+	EXYNOS_4212_UPHYPWR_HSCI1_PWR | \
+	EXYNOS_4212_UPHYPWR_HSCI1_SLEEP)
+
+/* PHY clock control */
+#define EXYNOS_421x_UPHYCLK			0x4
+
+#define EXYNOS_421x_UPHYCLK_PHY0_COMMON_ON	BIT(4)
+#define EXYNOS_421x_UPHYCLK_PHY1_COMMON_ON	BIT(7)
+
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_MASK	(0x3 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ	(0x0 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ	(0x3 << 0)
+#define EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
+
+#define EXYNOS_4210_UPHYCLK_PHY0_ID_PULLUP	BIT(2)
+
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_MASK	(0x7 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_9MHZ6	(0x0 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_10MHZ	(0x1 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_12MHZ	(0x2 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_19MHZ2	(0x3 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_20MHZ	(0x4 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_24MHZ	(0x5 << 0)
+#define EXYNOS_4212_UPHYCLK_PHYFSEL_50MHZ	(0x7 << 0)
+
+#define EXYNOS_4212_UPHYCLK_PHY0_ID_PULLUP	BIT(3)
+
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_MASK	(0x7f << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_12MHZ	(0x24 << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_15MHZ	(0x1c << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_16MHZ	(0x1a << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_19MHZ2	(0x15 << 10)
+#define EXYNOS_4212_UPHYCLK_HSIC_REFCLK_20MHZ	(0x14 << 10)
+
+/* PHY reset control */
+#define EXYNOS_421x_UPHYRST			0x8
+
+#define EXYNOS_421x_URSTCON_PHY0		BIT(0)
+#define EXYNOS_421x_URSTCON_OTG_HLINK		BIT(1)
+#define EXYNOS_421x_URSTCON_OTG_PHYLINK		BIT(2)
+
+#define EXYNOS_4210_URSTCON_PHY1_ALL		BIT(3)
+#define EXYNOS_4210_URSTCON_PHY1_P0		BIT(4)
+#define EXYNOS_4210_URSTCON_PHY1_P1P2		BIT(5)
+#define EXYNOS_4210_URSTCON_HOST_LINK_ALL	BIT(6)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P0	BIT(7)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P1	BIT(8)
+#define EXYNOS_4210_URSTCON_HOST_LINK_P2	BIT(9)
+
+#define EXYNOS_4212_URSTCON_HOST_PHY		BIT(3)
+#define EXYNOS_4212_URSTCON_PHY1		BIT(4)
+#define EXYNOS_4212_URSTCON_HSIC0		BIT(5)
+#define EXYNOS_4212_URSTCON_HSIC1		BIT(6)
+#define EXYNOS_4212_URSTCON_HOST_LINK_ALL	BIT(7)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P0	BIT(8)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P1	BIT(9)
+#define EXYNOS_4212_URSTCON_HOST_LINK_P2	BIT(10)
+
+/* Isolation, configured in the power management unit */
+#define EXYNOS_4210_USB_ISOL_DEVICE_OFFSET	0x704
+#define EXYNOS_4210_USB_ISOL_DEVICE		BIT(0)
+#define EXYNOS_4210_USB_ISOL_HOST_OFFSET	0x708
+#define EXYNOS_4210_USB_ISOL_HOST		BIT(0)
+
+#define EXYNOS_4212_USB_ISOL_OFFSET		0x704
+#define EXYNOS_4212_USB_ISOL_OTG		BIT(0)
+#define EXYNOS_4212_USB_ISOL_HSIC0_OFFSET	0x708
+#define EXYNOS_4212_USB_ISOL_HSIC0		BIT(0)
+#define EXYNOS_4212_USB_ISOL_HSIC1_OFFSET	0x70c
+#define EXYNOS_4212_USB_ISOL_HSIC1		BIT(0)
+
+/* USBYPHY1 Floating prevention */
+#define EXYNOS_4210_UPHY1CON			0x34
+#define EXYNOS_4210_UPHY1CON_FLOAT_PREVENTION	0x1
+
+/* Mode switching SUB Device <-> Host */
+#define EXYNOS_421x_MODE_SWITCH_OFFSET		0x21c
+#define EXYNOS_421x_MODE_SWITCH_MASK		1
+#define EXYNOS_421x_MODE_SWITCH_DEVICE		0
+#define EXYNOS_421x_MODE_SWITCH_HOST		1
+
+enum exynos421x_phy_id {
+	EXYNOS421x_DEVICE,
+	EXYNOS421x_HOST,
+	EXYNOS421x_HSIC0,
+	EXYNOS421x_HSIC1,
+	EXYNOS421x_NUM_PHYS,
+};
+
+/*
+ * exynos4210_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int exynos4210_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	switch (rate) {
+	case 12 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_12MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_24MHZ;
+		break;
+	case 48 * MHZ:
+		*reg = EXYNOS_4210_UPHYCLK_PHYFSEL_48MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * exynos4212_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static int exynos4212_rate_to_clk(unsigned long rate, u32 *reg)
+{
+	/* EXYNOS_4212_UPHYCLK_PHYFSEL_MASK */
+
+	switch (rate) {
+	case 9600 * KHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_9MHZ6;
+		break;
+	case 10 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_10MHZ;
+		break;
+	case 12 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_12MHZ;
+		break;
+	case 19200 * KHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_19MHZ2;
+		break;
+	case 20 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_20MHZ;
+		break;
+	case 24 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_24MHZ;
+		break;
+	case 50 * MHZ:
+		*reg = EXYNOS_4212_UPHYCLK_PHYFSEL_50MHZ;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void exynos421x_isol(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 offset;
+	u32 mask;
+
+	if (inst->cfg->is_exynos4212) {
+		switch (inst->cfg->id) {
+		case EXYNOS421x_DEVICE:
+		case EXYNOS421x_HOST:
+			offset = EXYNOS_4212_USB_ISOL_OFFSET;
+			mask = EXYNOS_4212_USB_ISOL_OTG;
+			break;
+		case EXYNOS421x_HSIC0:
+			offset = EXYNOS_4212_USB_ISOL_HSIC0_OFFSET;
+			mask = EXYNOS_4212_USB_ISOL_HSIC0;
+			break;
+		case EXYNOS421x_HSIC1:
+			offset = EXYNOS_4212_USB_ISOL_HSIC1_OFFSET;
+			mask = EXYNOS_4212_USB_ISOL_HSIC1;
+			break;
+		default:
+			return;
+		};
+	} else {
+		switch (inst->cfg->id) {
+		case EXYNOS421x_DEVICE:
+			offset = EXYNOS_4210_USB_ISOL_DEVICE_OFFSET;
+			mask = EXYNOS_4210_USB_ISOL_DEVICE;
+			break;
+		case EXYNOS421x_HOST:
+			offset = EXYNOS_4210_USB_ISOL_HOST_OFFSET;
+			mask = EXYNOS_4210_USB_ISOL_HOST;
+			break;
+		default:
+			return;
+		}
+	}
+
+	regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
+}
+
+static void exynos421x_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	u32 rstbits = 0;
+	u32 phypwr = 0;
+	u32 rst;
+	u32 pwr;
+
+	if (inst->cfg->is_exynos4212) {
+		switch (inst->cfg->id) {
+		case EXYNOS421x_DEVICE:
+			phypwr =	EXYNOS_421x_UPHYPWR_PHY0;
+			rstbits =	EXYNOS_421x_URSTCON_PHY0;
+			break;
+		case EXYNOS421x_HOST:
+			phypwr =	EXYNOS_421x_UPHYPWR_PHY1;
+			rstbits =	EXYNOS_4212_URSTCON_HOST_PHY;
+			break;
+		case EXYNOS421x_HSIC0:
+			phypwr =	EXYNOS_4212_UPHYPWR_HSCI0;
+			rstbits =	EXYNOS_4212_URSTCON_HSIC1 |
+					EXYNOS_4212_URSTCON_HOST_LINK_P0 |
+					EXYNOS_4212_URSTCON_HOST_PHY;
+			break;
+		case EXYNOS421x_HSIC1:
+			phypwr =	EXYNOS_4212_UPHYPWR_HSCI1;
+			rstbits =	EXYNOS_4212_URSTCON_HSIC1 |
+					EXYNOS_4212_URSTCON_HOST_LINK_P1;
+			break;
+		};
+	} else {
+		switch (inst->cfg->id) {
+		case EXYNOS421x_DEVICE:
+			phypwr =	EXYNOS_421x_UPHYPWR_PHY0;
+			rstbits =	EXYNOS_421x_URSTCON_PHY0;
+			break;
+		case EXYNOS421x_HOST:
+			phypwr =	EXYNOS_421x_UPHYPWR_PHY1;
+			rstbits =	EXYNOS_4210_URSTCON_PHY1_ALL |
+					EXYNOS_4210_URSTCON_PHY1_P0 |
+					EXYNOS_4210_URSTCON_PHY1_P1P2 |
+					EXYNOS_4210_URSTCON_HOST_LINK_ALL |
+					EXYNOS_4210_URSTCON_HOST_LINK_P0;
+			writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON);
+			break;
+		case EXYNOS421x_HSIC0:
+			phypwr =	EXYNOS_4210_UPHYPWR_HSCI0;
+			rstbits =	EXYNOS_4210_URSTCON_PHY1_P1P2 |
+					EXYNOS_4210_URSTCON_HOST_LINK_P1;
+			break;
+		case EXYNOS421x_HSIC1:
+			phypwr =	EXYNOS_4210_UPHYPWR_HSCI1;
+			rstbits =	EXYNOS_4210_URSTCON_PHY1_P1P2 |
+					EXYNOS_4210_URSTCON_HOST_LINK_P2;
+			break;
+		};
+	}
+
+	if (on) {
+		writel(inst->clk_reg_val, drv->reg_phy + EXYNOS_421x_UPHYCLK);
+
+		pwr = readl(drv->reg_phy + EXYNOS_421x_UPHYPWR);
+		pwr &= ~phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_421x_UPHYPWR);
+
+		rst = readl(drv->reg_phy + EXYNOS_421x_UPHYRST);
+		rst |= rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_421x_UPHYRST);
+		udelay(10);
+		rst &= ~rstbits;
+		writel(rst, drv->reg_phy + EXYNOS_421x_UPHYRST);
+	} else {
+		pwr = readl(drv->reg_phy + EXYNOS_421x_UPHYPWR);
+		pwr |= phypwr;
+		writel(pwr, drv->reg_phy + EXYNOS_421x_UPHYPWR);
+	}
+}
+
+static int exynos421x_power_on(struct samsung_usb2_phy_instance *inst)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+
+	inst->enabled = 1;
+	exynos421x_phy_pwr(inst, 1);
+	exynos421x_isol(inst, 0);
+
+	/* Power on the device, as it is necessary for HSIC to work */
+	if (inst->cfg->is_exynos4212 && inst->cfg->id == EXYNOS421x_HSIC0) {
+		struct samsung_usb2_phy_instance *device =
+					&drv->instances[EXYNOS421x_DEVICE];
+		exynos421x_phy_pwr(device, 1);
+		exynos421x_isol(device, 0);
+	}
+
+	return 0;
+}
+
+static int exynos421x_power_off(struct samsung_usb2_phy_instance *inst)
+{
+	struct samsung_usb2_phy_driver *drv = inst->drv;
+	struct samsung_usb2_phy_instance *device =
+					&drv->instances[EXYNOS421x_DEVICE];
+
+	inst->enabled = 0;
+	exynos421x_isol(inst, 1);
+	exynos421x_phy_pwr(inst, 0);
+
+	if (inst->cfg->is_exynos4212 && inst->cfg->id == EXYNOS421x_HSIC0 &&
+							!device->enabled) {
+		exynos421x_isol(device, 1);
+		exynos421x_phy_pwr(device, 0);
+	}
+
+	return 0;
+}
+
+static const struct samsung_usb2_common_phy exynos4210_phys[] = {
+	{
+		.label		= "device",
+		.id		= EXYNOS421x_DEVICE,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+	},
+	{
+		.label		= "host",
+		.id		= EXYNOS421x_HOST,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+	},
+	{
+		.label		= "hsic0",
+		.id		= EXYNOS421x_HSIC0,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+	},
+	{
+		.label		= "hsic1",
+		.id		= EXYNOS421x_HSIC1,
+		.rate_to_clk	= exynos4210_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+	},
+	{},
+};
+
+const struct samsung_usb2_phy_config exynos4210_usb2_phy_config = {
+	.num_phys		= EXYNOS421x_NUM_PHYS,
+	.phys			= exynos4210_phys,
+	.has_mode_switch	= 1,
+};
+
+static const struct samsung_usb2_common_phy exynos4212_phys[] = {
+	{
+		.label		= "device",
+		.id		= EXYNOS421x_DEVICE,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+		.is_exynos4212	= 1,
+	},
+	{
+		.label		= "host",
+		.id		= EXYNOS421x_HOST,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+		.is_exynos4212	= 1,
+	},
+	{
+		.label		= "hsic0",
+		.id		= EXYNOS421x_HSIC0,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+		.is_exynos4212	= 1,
+	},
+	{
+		.label		= "hsic1",
+		.id		= EXYNOS421x_HSIC1,
+		.rate_to_clk	= exynos4212_rate_to_clk,
+		.power_on	= exynos421x_power_on,
+		.power_off	= exynos421x_power_off,
+		.is_exynos4212	= 1,
+	},
+	{},
+};
+
+const struct samsung_usb2_phy_config exynos4212_usb2_phy_config = {
+	.num_phys		= EXYNOS421x_NUM_PHYS,
+	.phys			= exynos4212_phys,
+	.has_mode_switch	= 1,
+};
+
diff --git a/drivers/phy/phy-samsung-usb2.h b/drivers/phy/phy-samsung-usb2.h
index ab89f91..db02692 100644
--- a/drivers/phy/phy-samsung-usb2.h
+++ b/drivers/phy/phy-samsung-usb2.h
@@ -52,6 +52,7 @@ struct samsung_usb2_common_phy {
 	int (*power_off)(struct samsung_usb2_phy_instance *);
 	unsigned int id;
 	char *label;
+	bool is_exynos4212;
 };
 
 
