From patchwork Tue Jan 7 08:53:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tushar Behera X-Patchwork-Id: 3446331 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id BF3489F1C4 for ; Tue, 7 Jan 2014 08:57:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8F7CF2010C for ; Tue, 7 Jan 2014 08:57:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5602B2010B for ; Tue, 7 Jan 2014 08:57:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751610AbaAGI5n (ORCPT ); Tue, 7 Jan 2014 03:57:43 -0500 Received: from mail-pa0-f41.google.com ([209.85.220.41]:50631 "EHLO mail-pa0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751383AbaAGI5n (ORCPT ); Tue, 7 Jan 2014 03:57:43 -0500 Received: by mail-pa0-f41.google.com with SMTP id lf10so112379pab.28 for ; Tue, 07 Jan 2014 00:57:42 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=3rZweAQp5RN7y3QqkCs+0Ts/2/iq9LXqPAUc5M2CMwM=; b=iTme+WFgJ1/SXR5kZrAaoLAHuS6+pkuUgdG9m872I0Kbf7OJpUUYfwd4032uOKIi9D +VlGMxFe84z66oeoxl7Wx0K3CAWSM08gOkeoM80/7xmKozQHqo+IAwrvi8icSz9Wb+he +CKGmjs1wOst81zrPn72fuA3B/CPES2Tdf1cvDfklzvS3J0eT0DCMJ6Ink+rG5eu3MGS +CDY1Mcn0/e+3pWTPaCOHX6NM6d3TuA5HPL2/+Tq/1IYCKWviZ2uXnkrU0Q3cSJIQIA2 kkeKWFjR4RKhZPbelxQjHg+rhNAnfmLCCq6EUwuVpTKHohfJIK/hx4ANXWmRuN+J7t5R LnZw== X-Gm-Message-State: ALoCoQnRBTRGW6vfrDVQBFh1ttG+UBEYMmr39OHIHFN+nV63wolNdUU+g1RSJ2fnBu8co2g9t0HX X-Received: by 10.68.212.102 with SMTP id nj6mr30862615pbc.95.1389085062735; Tue, 07 Jan 2014 00:57:42 -0800 (PST) Received: from linaro.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPSA id y9sm175937061pas.10.2014.01.07.00.57.40 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 07 Jan 2014 00:57:42 -0800 (PST) From: Tushar Behera To: linux-samsung-soc@vger.kernel.org Cc: kgene.kim@samsung.com, arnd@arndb.de, tomasz.figa@gmail.com Subject: [PATCH] ARM: dts: Add l2x0 device node for Exynos4-based boards Date: Tue, 7 Jan 2014 14:23:46 +0530 Message-Id: <1389084826-19827-1-git-send-email-tushar.behera@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP For Exynos4 platform, L2 cache initialization is done only if a device node for l2x0 device exists. L2 cache initialization path is different when a board boots with secure firmware. Since there are many Exynos4 based SoCs that boot in secure mode, enabling this only for boards that don't boot with secure firmware. Signed-off-by: Tushar Behera --- Tested on Exynos4210-Origen board. arch/arm/boot/dts/exynos4.dtsi | 8 ++++++++ arch/arm/boot/dts/exynos4210-origen.dts | 4 ++++ arch/arm/boot/dts/exynos4210-smdkv310.dts | 4 ++++ arch/arm/boot/dts/exynos4210-trats.dts | 4 ++++ arch/arm/boot/dts/exynos4210-universal_c210.dts | 4 ++++ arch/arm/boot/dts/exynos4412-odroidx.dts | 4 ++++ arch/arm/boot/dts/exynos4412-smdk4412.dts | 4 ++++ arch/arm/boot/dts/exynos4412-tiny4412.dts | 4 ++++ 8 files changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 08452e1..e0ddbd2 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -49,6 +49,14 @@ reg = <0x10000000 0x100>; }; + l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + status = "disabled"; + }; + mipi_phy: video-phy@10020710 { compatible = "samsung,s5pv210-mipi-video-phy"; reg = <0x10020710 8>; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 2aa13cb..eea1286 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -32,6 +32,10 @@ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; + l2-cache-controller@10502000 { + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 9c01b71..5ce2869 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -29,6 +29,10 @@ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; }; + l2-cache-controller@10502000 { + status = "okay"; + }; + sdhci@12530000 { bus-width = <4>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 63cc571..00dbc6c 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -30,6 +30,10 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; }; + l2-cache-controller@10502000 { + status = "okay"; + }; + regulators { compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d2e3f5f..e732afe 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -28,6 +28,10 @@ bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1"; }; + l2-cache-controller@10502000 { + status = "okay"; + }; + mct@10050000 { compatible = "none"; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 8aad5f7..6fb9e84 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -22,6 +22,10 @@ reg = <0x40000000 0x40000000>; }; + l2-cache-controller@10502000 { + status = "okay"; + }; + leds { compatible = "gpio-leds"; led1 { diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index ad316a1..f72d425 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -27,6 +27,10 @@ bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc"; }; + l2-cache-controller@10502000 { + status = "okay"; + }; + g2d@10800000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index 0a98312..33a3cb89 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -22,6 +22,10 @@ reg = <0x40000000 0x40000000>; }; + l2-cache-controller@10502000 { + status = "okay"; + }; + leds { compatible = "gpio-leds";