From patchwork Tue Jan 7 12:59:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Sharma X-Patchwork-Id: 3447941 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 38865C02DE for ; Tue, 7 Jan 2014 13:01:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 838FF20120 for ; Tue, 7 Jan 2014 13:01:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 27F422010B for ; Tue, 7 Jan 2014 13:01:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751745AbaAGNBB (ORCPT ); Tue, 7 Jan 2014 08:01:01 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:56872 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751861AbaAGNAt (ORCPT ); Tue, 7 Jan 2014 08:00:49 -0500 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MZ1006NF84TIC00@mailout1.samsung.com>; Tue, 07 Jan 2014 22:00:29 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 1A.19.12635.C6AFBC25; Tue, 07 Jan 2014 22:00:29 +0900 (KST) X-AuditID: cbfee68d-b7fcd6d00000315b-fe-52cbfa6ccca3 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 5A.59.28157.C6AFBC25; Tue, 07 Jan 2014 22:00:28 +0900 (KST) Received: from localhost.localdomain ([107.108.83.245]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MZ10091R83QNV20@mmp2.samsung.com>; Tue, 07 Jan 2014 22:00:28 +0900 (KST) From: Rahul Sharma To: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: mturquette@linaro.org, kgene.kim@samsung.com, thomas.ab@samsung.com, tomasz.figa@gmail.com, joshi@samsung.com, r.sh.open@gmail.com, Pankaj Dubey , Rahul Sharma Subject: [PATCH V2 05/10] clk/samsung: add support for pll2550xx Date: Tue, 07 Jan 2014 18:29:03 +0530 Message-id: <1389099548-14649-6-git-send-email-rahul.sharma@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1389099548-14649-1-git-send-email-rahul.sharma@samsung.com> References: <1389099548-14649-1-git-send-email-rahul.sharma@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpnkeLIzCtJLcpLzFFi42JZI2JSo5v763SQwaEvjBbzj5xjtfi+6wu7 Re+Cq2wWmx5fY7WYcX4fk8XTCRfZLBZtBUosfBFvMWXRYVaLjmWMFqt2/WF04PbYOesuu8ed a3vYPDYvqffo27KK0ePzJrkA1igum5TUnMyy1CJ9uwSujHtnv7MWvFapWHD6KmsD4x65LkZO DgkBE4nOn9uYIGwxiQv31rN1MXJxCAksZZSY3POdGaZoz4nXzBCJ6YwSEy+uZYFw2pkkun/9 AqtiE9CVmH3wGWMXIweHiECmxMYtuSA1zAL3GCVOb54AtkJYwEFi7YpTYDaLgKrE7UdtrCA2 r4CHxP8Pv1lBeiUEFCTmTLIBCXMKeEocnNHMDmILAZU8fXIZ7AgJgV3sEmuOP4KaIyDxbfIh FoheWYlNB6COlpQ4uOIGywRG4QWMDKsYRVMLkguKk9KLDPWKE3OLS/PS9ZLzczcxAiPh9L9n vTsYbx+wPsSYDDRuIrOUaHI+MJLySuINjc2MLExNTI2NzC3NSBNWEudNepgUJCSQnliSmp2a WpBaFF9UmpNafIiRiYNTqoHRznuD1dWm3yG2RQ4hZowedZlHVd9tC99Ut391oddHhT4tj4ta ksIqUbNl68xY5J86Jq65bDQ76x7niv0uC5KO3tMK329zc7n9zPZUv707/ZrX1rVMtp2dfSru S96PyrOaJpsLNBt0JA8HJrgvXKC+5VqMjV9ByKnTua9/lEZanZow7XDHm4lKLMUZiYZazEXF iQDcSGXNmgIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrCIsWRmVeSWpSXmKPExsVy+t9jQd2cX6eDDFYfN7GYf+Qcq8X3XV/Y LXoXXGWz2PT4GqvFjPP7mCyeTrjIZrFoK1Bi4Yt4iymLDrNadCxjtFi16w+jA7fHzll32T3u XNvD5rF5Sb1H35ZVjB6fN8kFsEY1MNpkpCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqY KynkJeam2iq5+AToumXmAB2mpFCWmFMKFApILC5W0rfDNCE0xE3XAqYxQtc3JAiux8gADSSs Ycy4d/Y7a8FrlYoFp6+yNjDuketi5OSQEDCR2HPiNTOELSZx4d56ti5GLg4hgemMEhMvrmWB cNqZJLp//QKrYhPQlZh98BljFyMHh4hApsTGLbkgNcwC9xglTm+ewARSIyzgILF2xSkwm0VA VeL2ozZWEJtXwEPi/4ffrCC9EgIKEnMm2YCEOQU8JQ7OaGYHsYWASp4+ucw8gZF3ASPDKkbR 1ILkguKk9FwjveLE3OLSvHS95PzcTYzgOHsmvYNxVYPFIUYBDkYlHt4Xe08FCbEmlhVX5h5i lOBgVhLhZb5xOkiINyWxsiq1KD++qDQntfgQYzLQUROZpUST84EpIK8k3tDYxNzU2NTSxMLE zJI0YSVx3oOt1oFCAumJJanZqakFqUUwW5g4OKUaGNNmXHzYq5z0I1oj39dMR1rlzSv+/FkF +vumC2rt5vS1UIjkuOGke17q75a3iT+u2eUyRW3qMj63b6V0F+tPNYOu3NlfL4u29GYf3n6t LLOirGf9zhefZwo+vqZ47dd1ox3t1hNXK0zNj7xg6CKpqRrzXyTaf393/suNM23/B7PWx217 kPFRWYmlOCPRUIu5qDgRADe2biD3AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Pankaj Dubey exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here. Signed-off-by: Pankaj Dubey Signed-off-by: Rahul Sharma Signed-off-by: Arun Kumar K Acked-by: Tomasz Figa --- drivers/clk/samsung/clk-pll.c | 108 +++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 109 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index e8e8953..08f85ae 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -710,6 +710,108 @@ struct clk * __init samsung_clk_register_pll2550x(const char *name, return clk; } +/* + * PLL2550xx Clock Type + */ + +/* Maximum lock time can be 270 * PDIV cycles */ +#define PLL2550XX_LOCK_FACTOR 270 + +#define PLL2550XX_M_MASK 0x3FF +#define PLL2550XX_P_MASK 0x3F +#define PLL2550XX_S_MASK 0x7 +#define PLL2550XX_LOCK_STAT_MASK 0x1 +#define PLL2550XX_M_SHIFT 9 +#define PLL2550XX_P_SHIFT 3 +#define PLL2550XX_S_SHIFT 0 +#define PLL2550XX_LOCK_STAT_SHIFT 21 + +static unsigned long samsung_pll2550xx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, pll_con; + u64 fvco = parent_rate; + + pll_con = __raw_readl(pll->con_reg); + mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; + pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; + sdiv = (pll_con >> PLL2550XX_S_SHIFT) & PLL2550XX_S_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + + return (unsigned long)fvco; +} + +static inline bool samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) +{ + u32 old_mdiv, old_pdiv; + + old_mdiv = (pll_con >> PLL2550XX_M_SHIFT) & PLL2550XX_M_MASK; + old_pdiv = (pll_con >> PLL2550XX_P_SHIFT) & PLL2550XX_P_MASK; + + return mdiv != old_mdiv || pdiv != old_pdiv; +} + +static int samsung_pll2550xx_set_rate(struct clk_hw *hw, unsigned long drate, + unsigned long prate) +{ + struct samsung_clk_pll *pll = to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 tmp; + + /* Get required rate settings from table */ + rate = samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, __clk_get_name(hw->clk)); + return -EINVAL; + } + + tmp = __raw_readl(pll->con_reg); + + if (!(samsung_pll2550xx_mp_change(rate->mdiv, rate->pdiv, tmp))) { + /* If only s change, change just s value only*/ + tmp &= ~(PLL2550XX_S_MASK << PLL2550XX_S_SHIFT); + tmp |= rate->sdiv << PLL2550XX_S_SHIFT; + __raw_writel(tmp, pll->con_reg); + + return 0; + } + + /* Set PLL lock time. */ + __raw_writel(rate->pdiv * PLL2550XX_LOCK_FACTOR, pll->lock_reg); + + /* Change PLL PMS values */ + tmp &= ~((PLL2550XX_M_MASK << PLL2550XX_M_SHIFT) | + (PLL2550XX_P_MASK << PLL2550XX_P_SHIFT) | + (PLL2550XX_S_MASK << PLL2550XX_S_SHIFT)); + tmp |= (rate->mdiv << PLL2550XX_M_SHIFT) | + (rate->pdiv << PLL2550XX_P_SHIFT) | + (rate->sdiv << PLL2550XX_S_SHIFT); + __raw_writel(tmp, pll->con_reg); + + /* wait_lock_time */ + do { + cpu_relax(); + tmp = __raw_readl(pll->con_reg); + } while (!(tmp & (PLL2550XX_LOCK_STAT_MASK + << PLL2550XX_LOCK_STAT_SHIFT))); + + return 0; +} + +static const struct clk_ops samsung_pll2550xx_clk_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, + .round_rate = samsung_pll_round_rate, + .set_rate = samsung_pll2550xx_set_rate, +}; + +static const struct clk_ops samsung_pll2550xx_clk_min_ops = { + .recalc_rate = samsung_pll2550xx_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, struct samsung_pll_clock *pll_clk, void __iomem *base) @@ -787,6 +889,12 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, else init.ops = &samsung_pll46xx_clk_ops; break; + case pll_2550xx: + if (!pll->rate_table) + init.ops = &samsung_pll2550xx_clk_min_ops; + else + init.ops = &samsung_pll2550xx_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 6c39030..e106470 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -25,6 +25,7 @@ enum samsung_pll_type { pll_4650c, pll_6552, pll_6553, + pll_2550xx, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \