From patchwork Fri Mar 21 12:02:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuvaraj CD X-Patchwork-Id: 3873421 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id E2482BF540 for ; Fri, 21 Mar 2014 12:02:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 116CE2027D for ; Fri, 21 Mar 2014 12:02:42 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E8164201C0 for ; Fri, 21 Mar 2014 12:02:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759943AbaCUMCj (ORCPT ); Fri, 21 Mar 2014 08:02:39 -0400 Received: from mail-pd0-f171.google.com ([209.85.192.171]:62797 "EHLO mail-pd0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758075AbaCUMCj (ORCPT ); Fri, 21 Mar 2014 08:02:39 -0400 Received: by mail-pd0-f171.google.com with SMTP id r10so2245307pdi.16 for ; Fri, 21 Mar 2014 05:02:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=DWwlKnrDsklo6cuw2rznBOPshjFMTapyh+QIfBHAVFg=; b=w5b2uFYUyI+k097cbvLz58Gm2ji8cvWxkqN0Pirn4j40PHZIOlqAoetsPx9U2wziWN QSc2siWYJXQAcYlYhC5H56XamnpatQZSOSS7KxW0urtNmHru7X5OnmQHCKV4YTSJ9V1g 87WJmwmv41rqqneRAE4br4KJd3WIXEDxNK9VRxUvRIYkP9r7SGnMxVxjv9tv/fqvABGk 19jluqLsyvMAMyz4ZSsYhrHcxAmhma0qYAA0UquHPC5REn/T75Aj6Dh9vIhyrj+bOHnC xcnB8kcMl9POvyGVOhYK46If9Rz1RIS+tNtSVh2UGK2TIDGjVOGPzipxFIOtmHIVahTf R5Qw== X-Received: by 10.66.250.161 with SMTP id zd1mr31111341pac.136.1395403348975; Fri, 21 Mar 2014 05:02:28 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id y4sm9528262pbk.76.2014.03.21.05.02.22 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 21 Mar 2014 05:02:28 -0700 (PDT) From: Yuvaraj Kumar C D To: grundler@chromium.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jh80.chung@samsung.com, cjb@laptop.org, tgih.jun@samsung.com, linux-mmc@vger.kernel.org, sonnyrao@chromium.org, kgene.kim@samsung.com, joshi@samsung.com Cc: t.figa@samsung.com, Doug Anderson , Yuvaraj Kumar C D Subject: [PATCH] mmc: dw_mmc: Support setting the ciu-div on exynos Date: Fri, 21 Mar 2014 17:32:07 +0530 Message-Id: <1395403327-19713-1-git-send-email-yuvaraj.cd@samsung.com> X-Mailer: git-send-email 1.7.10.4 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Doug Anderson The existing dw_mmc code for exynos5250/exynos5420 read the ciu-div property from the device tree and used it in calculations, but didn't actually ever set it in hardware. That means that if the hardware value set by the firmware didn't match what was in the device tree that we'd be clocking things incorrectly. Signed-off-by: Doug Anderson Signed-off-by: Yuvaraj Kumar C D --- drivers/mmc/host/dw_mmc-exynos.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 3423c5e..07392ac 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -28,6 +28,7 @@ #define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0) #define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16) #define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24) +#define SDMMC_CLKSEL_GET_SAMPLE(x) (((x) >> 0) & 0x7) #define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7) #define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \ SDMMC_CLKSEL_CCLK_DRIVE(y) | \ @@ -118,6 +119,12 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host) { struct dw_mci_exynos_priv_data *priv = host->priv; unsigned long rate = clk_get_rate(host->ciu_clk); + u32 clksel = mci_readl(host, CLKSEL); + + clksel = SDMMC_CLKSEL_TIMING(SDMMC_CLKSEL_GET_SAMPLE(clksel), + SDMMC_CLKSEL_GET_DRV_WD3(clksel), + priv->ciu_div); + mci_writel(host, CLKSEL, clksel); host->bus_hz = rate / (priv->ciu_div + 1); return 0;