From patchwork Fri Apr 4 07:47:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 3936921 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AD0A5C0DA2 for ; Fri, 4 Apr 2014 07:48:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A0FBE203E1 for ; Fri, 4 Apr 2014 07:48:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A98F7203E9 for ; Fri, 4 Apr 2014 07:48:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752184AbaDDHsH (ORCPT ); Fri, 4 Apr 2014 03:48:07 -0400 Received: from mail-wg0-f47.google.com ([74.125.82.47]:33992 "EHLO mail-wg0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752162AbaDDHsG (ORCPT ); Fri, 4 Apr 2014 03:48:06 -0400 Received: by mail-wg0-f47.google.com with SMTP id x12so2996865wgg.6 for ; Fri, 04 Apr 2014 00:48:04 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=/BIHzw8/J4eMTxz9uv2FfsyOfOA0O3or6/VfsEelsxI=; b=eWJYvnO/pNKnxCy9bfZvv+6tsau3qaE2bk5vGyz7vIZwFyYOnIQgE7tXDITomGgRAs bEB4K8VzrcmFecFbaPIQrwlB5Hv6CnLhMBYylNpjAOI7vPPEqkL6/26W4d2O3VMQOuGt AuJ/IFRqPyrZ9/HbfGuXYIH0nIPIdN7nrMVoG+IYGoke6sK3fhl+GqqNAUlnktMRRATY LkEqtmqOpIY1/G89Y2Ioy2eS/JIh1/uKHEv9ts8XLS7J992ZADEJTVJ5hHEdMKXpNt0J j1wuBWaGbHYTo4/KYoECeFUMQs9IaY2+tfsgXdqIKedEM231gSaPGyNzyyocv47axpHQ 7KUA== X-Gm-Message-State: ALoCoQkNZxvuW8a3MqcBJSXmHTPEmWiyjemH12nR1y2UPV4hqAHlB38FsYqeHrvM86ZV6XWvm3VR X-Received: by 10.180.221.68 with SMTP id qc4mr2261150wic.30.1396597684931; Fri, 04 Apr 2014 00:48:04 -0700 (PDT) Received: from localhost.localdomain (AToulouse-654-1-451-172.w83-205.abo.wanadoo.fr. [83.205.74.172]) by mx.google.com with ESMTPSA id t1sm3028163wia.1.2014.04.04.00.48.03 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 04 Apr 2014 00:48:03 -0700 (PDT) From: Daniel Lezcano To: kgene.kim@samsung.com Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, t.figa@samsung.com, linaro-kernel@lists.linaro.org, rjw@rjwysocki.net Subject: [PATCH 13/17] ARM: exynos: cpuidle: Move clock setup to pm.c Date: Fri, 4 Apr 2014 09:47:59 +0200 Message-Id: <1396597683-6969-14-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1396597683-6969-1-git-send-email-daniel.lezcano@linaro.org> References: <1396597683-6969-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP One more step is moving the clock ratio setting at idle time in pm.c The macro names have been changed to be consistent with the other macros name in the file. Note, the clock divider was working only when cpuidle was enabled because it was in its init routine. With this change, the clock divider is set in the pm's init routine, so it will also operate when the cpuidle driver is not set, which is good. Signed-off-by: Daniel Lezcano Reviewed-by: Viresh Kumar --- arch/arm/mach-exynos/cpuidle.c | 54 --------------------------------------- arch/arm/mach-exynos/pm.c | 55 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 55 deletions(-) diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index 839185e..3872c1e 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -38,25 +38,6 @@ S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1)) -#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020) -#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024) - -#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) -#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) -#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) -#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) -#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) -#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) -#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) -#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) - -#define PWR_CTRL2_DIV2_UP_EN (1 << 25) -#define PWR_CTRL2_DIV1_UP_EN (1 << 24) -#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) -#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) -#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) -#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) - static int idle_finisher(unsigned long flags) { @@ -98,38 +79,6 @@ static int exynos_enter_lowpower(struct cpuidle_device *dev, return exynos_enter_core0_aftr(dev, drv, new_index); } -static void __init exynos5_core_down_clk(void) -{ - unsigned int tmp; - - /* - * Enable arm clock down (in idle) and set arm divider - * ratios in WFI/WFE state. - */ - tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \ - PWR_CTRL1_CORE1_DOWN_RATIO | \ - PWR_CTRL1_DIV2_DOWN_EN | \ - PWR_CTRL1_DIV1_DOWN_EN | \ - PWR_CTRL1_USE_CORE1_WFE | \ - PWR_CTRL1_USE_CORE0_WFE | \ - PWR_CTRL1_USE_CORE1_WFI | \ - PWR_CTRL1_USE_CORE0_WFI; - __raw_writel(tmp, EXYNOS5_PWR_CTRL1); - - /* - * Enable arm clock up (on exiting idle). Set arm divider - * ratios when not in idle along with the standby duration - * ratios. - */ - tmp = PWR_CTRL2_DIV2_UP_EN | \ - PWR_CTRL2_DIV1_UP_EN | \ - PWR_CTRL2_DUR_STANDBY2_VAL | \ - PWR_CTRL2_DUR_STANDBY1_VAL | \ - PWR_CTRL2_CORE2_UP_RATIO | \ - PWR_CTRL2_CORE1_UP_RATIO; - __raw_writel(tmp, EXYNOS5_PWR_CTRL2); -} - static struct cpuidle_driver exynos_idle_driver = { .name = "exynos_idle", .owner = THIS_MODULE, @@ -152,9 +101,6 @@ static int exynos_cpuidle_probe(struct platform_device *pdev) { int ret; - if (soc_is_exynos5250()) - exynos5_core_down_clk(); - if (soc_is_exynos5440()) exynos_idle_driver.state_count = 1; diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index b364212..1c9d253 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -60,6 +60,25 @@ #define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338) +#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020) +#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024) + +#define EXYNOS5_PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) +#define EXYNOS5_PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) +#define EXYNOS5_PWR_CTRL1_DIV2_DOWN_EN (1 << 9) +#define EXYNOS5_PWR_CTRL1_DIV1_DOWN_EN (1 << 8) +#define EXYNOS5_PWR_CTRL1_USE_CORE1_WFE (1 << 5) +#define EXYNOS5_PWR_CTRL1_USE_CORE0_WFE (1 << 4) +#define EXYNOS5_PWR_CTRL1_USE_CORE1_WFI (1 << 1) +#define EXYNOS5_PWR_CTRL1_USE_CORE0_WFI (1 << 0) + +#define EXYNOS5_PWR_CTRL2_DIV2_UP_EN (1 << 25) +#define EXYNOS5_PWR_CTRL2_DIV1_UP_EN (1 << 24) +#define EXYNOS5_PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) +#define EXYNOS5_PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) +#define EXYNOS5_PWR_CTRL2_CORE2_UP_RATIO (1 << 4) +#define EXYNOS5_PWR_CTRL2_CORE1_UP_RATIO (1 << 0) + static const struct sleep_save exynos4_set_clksrc[] = { { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, @@ -99,7 +118,6 @@ static struct sleep_save exynos_core_save[] = { SAVE_ITEM(S5P_SROM_BC3), }; - /* For Cortex-A9 Diagnostic and Power control register */ static unsigned int save_arm_register[2]; @@ -139,6 +157,38 @@ static void exynos_cpu_restore_register(void) : "cc"); } +static void __init exynos5_core_down_clk(void) +{ + unsigned int tmp; + + /* + * Enable arm clock down (in idle) and set arm divider + * ratios in WFI/WFE state. + */ + tmp = EXYNOS5_PWR_CTRL1_CORE2_DOWN_RATIO | \ + EXYNOS5_PWR_CTRL1_CORE1_DOWN_RATIO | \ + EXYNOS5_PWR_CTRL1_DIV2_DOWN_EN | \ + EXYNOS5_PWR_CTRL1_DIV1_DOWN_EN | \ + EXYNOS5_PWR_CTRL1_USE_CORE1_WFE | \ + EXYNOS5_PWR_CTRL1_USE_CORE0_WFE | \ + EXYNOS5_PWR_CTRL1_USE_CORE1_WFI | \ + EXYNOS5_PWR_CTRL1_USE_CORE0_WFI; + __raw_writel(tmp, EXYNOS5_PWR_CTRL1); + + /* + * Enable arm clock up (on exiting idle). Set arm divider + * ratios when not in idle along with the standby duration + * ratios. + */ + tmp = EXYNOS5_PWR_CTRL2_DIV2_UP_EN | \ + EXYNOS5_PWR_CTRL2_DIV1_UP_EN | \ + EXYNOS5_PWR_CTRL2_DUR_STANDBY2_VAL | \ + EXYNOS5_PWR_CTRL2_DUR_STANDBY1_VAL | \ + EXYNOS5_PWR_CTRL2_CORE2_UP_RATIO | \ + EXYNOS5_PWR_CTRL2_CORE1_UP_RATIO; + __raw_writel(tmp, EXYNOS5_PWR_CTRL2); +} + static int exynos_cpu_suspend(unsigned long arg) { #ifdef CONFIG_CACHE_L2X0 @@ -425,6 +475,9 @@ static __init int exynos_pm_syscore_init(void) if (soc_is_exynos5440()) return 0; + if (soc_is_exynos5250()) + exynos5_core_down_clk(); + if (!soc_is_exynos5250()) cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);