From patchwork Tue Apr 15 16:30:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 3994111 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 632AD9F2CC for ; Tue, 15 Apr 2014 16:30:40 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8931720266 for ; Tue, 15 Apr 2014 16:30:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 14D6F2025B for ; Tue, 15 Apr 2014 16:30:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751192AbaDOQah (ORCPT ); Tue, 15 Apr 2014 12:30:37 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:57872 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751019AbaDOQag (ORCPT ); Tue, 15 Apr 2014 12:30:36 -0400 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0N42004S5Z6YS810@mailout4.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 16 Apr 2014 01:30:34 +0900 (KST) X-AuditID: cbfee61a-b7fb26d00000724f-e6-534d5eaae9cd Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 9E.7C.29263.AAE5D435; Wed, 16 Apr 2014 01:30:34 +0900 (KST) Received: from amdc1344.digital.local ([106.116.147.32]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0N42004YIZ6QW340@mmp2.samsung.com>; Wed, 16 Apr 2014 01:30:34 +0900 (KST) From: Sylwester Nawrocki To: t.figa@samsung.com Cc: mturquette@linaro.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sylwester Nawrocki Subject: [PATCH] clk: exynos4: Use single clock ID for CLK_MDMA gate clocks Date: Tue, 15 Apr 2014 18:30:20 +0200 Message-id: <1397579420-18776-1-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrDJMWRmVeSWpSXmKPExsVy+t9jQd1Vcb7BBp8OyFtsenyN1WLG+X1M Fk8nXGSzOPymndVi/YzXLA6sHneu7WHz2Lyk3qNvyypGj8+b5AJYorhsUlJzMstSi/TtErgy pm75yVZwlL/ieesMtgbGebxdjJwcEgImEnMv/WCEsMUkLtxbz9bFyMUhJDCdUWLpt0ZmCKeD SeLq0/usIFVsAoYSvUf7wDpEgDq+TlwMVsQsMJlR4vPjDWAJYQFviYPv/oM1sAioSkxsWwcW 5xVwkzh/shXI5gBapyAxZ5LNBEbuBYwMqxhFUwuSC4qT0nMN9YoTc4tL89L1kvNzNzGCw+CZ 1A7GlQ0WhxgFOBiVeHg9JvgEC7EmlhVX5h5ilOBgVhLh/cjtGyzEm5JYWZValB9fVJqTWnyI UZqDRUmc90CrdaCQQHpiSWp2ampBahFMlomDU6qBUbr3/LTnDQmNSm/mLPm9vk/9fqfBviVN OXkrFJNqBBiXHCgvZg+s6Hc8YNyrsWXX0wdPjykunXCh9aBO3e8Z/JN1g/SjPJl0vqydu8vu X3HVNxXdqMD3pxpCpEW1P528t2prZ4T6pH/TNyv8+zPF/hrPa711D4q6uC4pZ2m4LfGU2ll8 VlJ3ixJLcUaioRZzUXEiAJmCAq7/AQAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock defined exactly in same way in documentation. Using different names for these clocks is a bit misleading. Since there is no users of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA has correct clock assigned on Exynos4x12 SoCs. Suggested-by: Tomasz Figa Signed-off-by: Sylwester Nawrocki Acked-by: Kyungmin Park --- drivers/clk/samsung/clk-exynos4.c | 2 +- include/dt-bindings/clock/exynos4.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index b4f9672..5247caa 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -903,7 +903,7 @@ static struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = { GATE(CLK_AUDSS, "audss", "sclk_epll", E4X12_GATE_IP_MAUDIO, 0, 0, 0), GATE(CLK_MDNIE0, "mdnie0", "aclk160", GATE_IP_LCD0, 2, 0, 0), GATE(CLK_ROTATOR, "rotator", "aclk200", E4X12_GATE_IP_IMAGE, 1, 0, 0), - GATE(CLK_MDMA2, "mdma2", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), + GATE(CLK_MDMA, "mdma", "aclk200", E4X12_GATE_IP_IMAGE, 2, 0, 0), GATE(CLK_SMMU_MDMA, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0), GATE(CLK_MIPI_HSI, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0), diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h index 75aff33..3ff13bc 100644 --- a/include/dt-bindings/clock/exynos4.h +++ b/include/dt-bindings/clock/exynos4.h @@ -181,7 +181,6 @@ #define CLK_KEYIF 347 #define CLK_AUDSS 348 #define CLK_MIPI_HSI 349 /* Exynos4210 only */ -#define CLK_MDMA2 350 /* Exynos4210 only */ #define CLK_PIXELASYNCM0 351 #define CLK_PIXELASYNCM1 352 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */