From patchwork Wed Aug 27 09:48:04 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 4786961 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id B1554C0338 for ; Wed, 27 Aug 2014 09:52:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ABE6720145 for ; Wed, 27 Aug 2014 09:52:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7539220123 for ; Wed, 27 Aug 2014 09:52:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933135AbaH0Jwb (ORCPT ); Wed, 27 Aug 2014 05:52:31 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:42241 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933090AbaH0Jwa (ORCPT ); Wed, 27 Aug 2014 05:52:30 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NAY001VVM3GZB90@mailout3.samsung.com> for linux-samsung-soc@vger.kernel.org; Wed, 27 Aug 2014 18:52:28 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.126]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 09.5C.04513.C5AADF35; Wed, 27 Aug 2014 18:52:28 +0900 (KST) X-AuditID: cbfee691-f79546d0000011a1-f8-53fdaa5c23da Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 81.90.04943.C5AADF35; Wed, 27 Aug 2014 18:52:28 +0900 (KST) Received: from chnaveen-ubuntu.sisodomain.com ([107.108.83.161]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NAY001Q2M382M10@mmp1.samsung.com>; Wed, 27 Aug 2014 18:52:28 +0900 (KST) From: Naveen Krishna Chatradhi Cc: naveenkrishna.ch@gmail.com, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, cpgs@samsung.com, Tomasz Figa , Mike Turquette , Thomas Abraham Subject: [PATCH 01/14] clk: samsung: add support for 145xx and 1460x PLLs Date: Wed, 27 Aug 2014 15:18:04 +0530 Message-id: <1409132889-2080-1-git-send-email-ch.naveen@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrALMWRmVeSWpSXmKPExsWyRsSkTjdm1d9gg+cv5C1eHtK02PT4GqvF jPP7mCyeTrjIZrFo239mi/UzXrNYdCxjdGD32DnrLrvHnWt72Dw2L6n36NuyitHj8ya5ANYo LpuU1JzMstQifbsErozLd7uZCpaYVby8PYO1gXGfThcjB4eEgInE7peaXYycQKaYxIV769m6 GLk4hASWMkpsvz2NGSJhIvHr2AZ2iMQiRolF3+ezQjj9TBJzL3exg1SxCZhJHFy0GswWEWCW WDD1PCNIEbPAR0aJ6+dPMoIkhAU8Jb69Xw42lkVAVeLJtl9MIDavgIvEilUfWSFOUpCYM8kG pFdC4D+bxNHFC1gh6gUkvk0+xAJRIyux6QDUdZISB1fcYJnAKLiAkWEVo2hqQXJBcVJ6kale cWJucWleul5yfu4mRmDAnv73bOIOxvsHrA8xCnAwKvHwfljwJ1iINbGsuDL3EKMp0IaJzFKi yfnAuMgriTc0NjOyMDUxNTYytzRTEufVkf4ZLCSQnliSmp2aWpBaFF9UmpNafIiRiYNTqoFR 8FREyNXbfQsOWVYsS/HuuH9C0NNrDU/76gmn/3RImx57sJeBP/2O0It9UsfrS1oyJeedMVF4 JS+bWSfuYCqyK1B3IeNv8Rneby9/VX7d7fRkxe938p/sz+t7TAqdOm/OdIGLFbMnfKlleZ/Q 8Pngzf1ajkGtQRd2/eTnXB2/1cP0cZqam0KcEktxRqKhFnNRcSIAoE3dX1MCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42I5/e+xgG7Mqr/BBlemiVm8PKRpsenxNVaL Gef3MVk8nXCRzWLRtv/MFutnvGax6FjG6MDusXPWXXaPO9f2sHlsXlLv0bdlFaPH501yAaxR DYw2GamJKalFCql5yfkpmXnptkrewfHO8aZmBoa6hpYW5koKeYm5qbZKLj4Bum6ZOUBHKCmU JeaUAoUCEouLlfTtME0IDXHTtYBpjND1DQmC6zEyQAMJaxgzLt/tZipYYlbx8vYM1gbGfTpd jJwcEgImEr+ObWCHsMUkLtxbz9bFyMUhJLCIUWLR9/msEE4/k8Tcy11gVWwCZhIHF60Gs0UE mCUWTD3PCFLELPCRUeL6+ZOMIAlhAU+Jb++XM4PYLAKqEk+2/WICsXkFXCRWrPoINJUDaJ2C xJxJNhMYuRcwMqxiFE0tSC4oTkrPNdQrTswtLs1L10vOz93ECI6IZ1I7GFc2WBxiFOBgVOLh /bjgT7AQa2JZcWXuIUYJDmYlEV72WX+DhXhTEiurUovy44tKc1KLDzGaAi2fyCwlmpwPjNa8 knhDYxNzU2NTSxMLEzNLJXHeA63WgUIC6YklqdmpqQWpRTB9TBycUg2MGgek4nv92pV84iJX ufteefTx1h5jrlmrJ56+rLjxif+2T8xvK/W11tcdX9d8qHwpa/zqFUcbxcM4Hs/ZfDS2MNH4 dsBdDh9trccBPf/PBy7kMU6fF+H8+XVGWdOMDymzLW/8028yzk+6uFrfyiHl2atSh/UTw9Uy 1jC3Why886RgvcUuQ/NUJZbijERDLeai4kQArJnhSZ4CAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected To: unlisted-recipients:; (no To-header on input) Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP By registers bits and offsets the 145xx PLL is similar to pll_type "pll_35xx". Also, 1460x PLL is similar to pll_type "pll_46xx". Hence, reusing the functions defined for pll_35xx and pll_46xx to support 145xx and 1460x PLLs respectively. Signed-off-by: Naveen Krishna Chatradhi Cc: Tomasz Figa Cc: Mike Turquette Cc: Thomas Abraham --- drivers/clk/samsung/clk-pll.c | 50 ++++++++++++++++++++++++++++++++--------- drivers/clk/samsung/clk-pll.h | 4 ++++ 2 files changed, 43 insertions(+), 11 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b07fad2..fe24e4d 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -130,6 +130,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = { */ /* Maximum lock time can be 270 * PDIV cycles */ #define PLL35XX_LOCK_FACTOR (270) +#define PLL145XX_LOCK_FACTOR (150) #define PLL35XX_MDIV_MASK (0x3FF) #define PLL35XX_PDIV_MASK (0x3F) @@ -139,6 +140,7 @@ static const struct clk_ops samsung_pll3000_clk_ops = { #define PLL35XX_PDIV_SHIFT (8) #define PLL35XX_SDIV_SHIFT (0) #define PLL35XX_LOCK_STAT_SHIFT (29) +#define PLL145XX_ENABLE BIT(31) static unsigned long samsung_pll35xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) @@ -186,6 +188,10 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, tmp = __raw_readl(pll->con_reg); + /* Enable PLL */ + if (pll->type == (pll_1450x || pll_1451x || pll_1452x)) + tmp |= PLL145XX_ENABLE; + if (!(samsung_pll35xx_mp_change(rate, tmp))) { /* If only s change, change just s value only*/ tmp &= ~(PLL35XX_SDIV_MASK << PLL35XX_SDIV_SHIFT); @@ -196,8 +202,12 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, unsigned long drate, } /* Set PLL lock time. */ - __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR, - pll->lock_reg); + if (pll->type == (pll_1450x || pll_1451x || pll_1452x)) + __raw_writel(rate->pdiv * PLL145XX_LOCK_FACTOR, + pll->lock_reg); + else + __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR, + pll->lock_reg); /* Change PLL PMS values */ tmp &= ~((PLL35XX_MDIV_MASK << PLL35XX_MDIV_SHIFT) | @@ -356,7 +366,6 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = { #define PLL45XX_ENABLE BIT(31) #define PLL45XX_LOCKED BIT(29) - static unsigned long samsung_pll45xx_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -482,6 +491,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = { #define PLL46XX_VSEL_MASK (1) #define PLL46XX_MDIV_MASK (0x1FF) +#define PLL1460X_MDIV_MASK (0x3FF) + #define PLL46XX_PDIV_MASK (0x3F) #define PLL46XX_SDIV_MASK (0x7) #define PLL46XX_VSEL_SHIFT (27) @@ -511,13 +522,14 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, pll_con0 = __raw_readl(pll->con_reg); pll_con1 = __raw_readl(pll->con_reg + 4); - mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; + mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? + PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; - kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : + kdiv = (pll->type == pll_4650c) ? pll_con1 & PLL4650C_KDIV_MASK : pll_con1 & PLL46XX_KDIV_MASK; - shift = pll->type == pll_4600 ? 16 : 10; + shift = (pll->type == (pll_4600 || pll_1460x)) ? 16 : 10; fvco *= (mdiv << shift) + kdiv; do_div(fvco, (pdiv << sdiv)); fvco >>= shift; @@ -526,11 +538,14 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, } static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1, - const struct samsung_pll_rate_table *rate) + const struct samsung_pll_rate_table *rate, + struct samsung_clk_pll *pll) { u32 old_mdiv, old_pdiv, old_kdiv; - old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; + old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & + ((pll->type == pll_1460x) ? + PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; old_kdiv = (pll_con1 >> PLL46XX_KDIV_SHIFT) & PLL46XX_KDIV_MASK; @@ -557,7 +572,7 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, con0 = __raw_readl(pll->con_reg); con1 = __raw_readl(pll->con_reg + 0x4); - if (!(samsung_pll46xx_mpk_change(con0, con1, rate))) { + if (!(samsung_pll46xx_mpk_change(con0, con1, rate, pll))) { /* If only s change, change just s value only*/ con0 &= ~(PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT); con0 |= rate->sdiv << PLL46XX_SDIV_SHIFT; @@ -573,14 +588,23 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, lock = 0xffff; /* Set PLL PMS and VSEL values. */ - con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + if (pll->type == pll_1460x) { + con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | + (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT)); + con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | + (rate->pdiv << PLL46XX_PDIV_SHIFT) | + (rate->sdiv << PLL46XX_SDIV_SHIFT); + } else { + con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) | (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT)); - con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | + con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | (rate->pdiv << PLL46XX_PDIV_SHIFT) | (rate->sdiv << PLL46XX_SDIV_SHIFT) | (rate->vsel << PLL46XX_VSEL_SHIFT); + } /* Set PLL K, MFR and MRR values. */ con1 = __raw_readl(pll->con_reg + 0x4); @@ -1190,6 +1214,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, /* clk_ops for 35xx and 2550 are similar */ case pll_35xx: case pll_2550: + case pll_1450x: + case pll_1451x: + case pll_1452x: if (!pll->rate_table) init.ops = &samsung_pll35xx_clk_min_ops; else @@ -1223,6 +1250,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_4600: case pll_4650: case pll_4650c: + case pll_1460x: if (!pll->rate_table) init.ops = &samsung_pll46xx_clk_min_ops; else diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index c0ed4d4..213de9a 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -33,6 +33,10 @@ enum samsung_pll_type { pll_s3c2440_mpll, pll_2550xx, pll_2650xx, + pll_1450x, + pll_1451x, + pll_1452x, + pll_1460x, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \