From patchwork Tue Sep 2 15:35:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 4826701 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 00C679F32F for ; Tue, 2 Sep 2014 15:41:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 11FE22017D for ; Tue, 2 Sep 2014 15:41:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1CFC3201BC for ; Tue, 2 Sep 2014 15:41:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753981AbaIBPld (ORCPT ); Tue, 2 Sep 2014 11:41:33 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:63190 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751735AbaIBPlc (ORCPT ); Tue, 2 Sep 2014 11:41:32 -0400 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NBA00B5Y696D620@mailout4.samsung.com>; Wed, 03 Sep 2014 00:41:30 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.122]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id BA.90.04442.A25E5045; Wed, 03 Sep 2014 00:41:30 +0900 (KST) X-AuditID: cbfee690-f79ce6d00000115a-35-5405e5292461 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id DB.DA.04943.925E5045; Wed, 03 Sep 2014 00:41:29 +0900 (KST) Received: from chnaveen-ubuntu.sisodomain.com ([107.108.83.161]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NBA002I96728OC0@mmp1.samsung.com>; Wed, 03 Sep 2014 00:41:29 +0900 (KST) From: Naveen Krishna Chatradhi To: linux-arm-kernel@lists.infradead.org Cc: naveenkrishna.ch@gmail.com, linux-samsung-soc@vger.kernel.org, catalin.marinas@arm.com, robh@kernel.org, devicetree@vger.kernel.org, t.figa@samsung.com, kgene.kim@samsung.com, Mike Turquette Subject: [PATCH v2 1/7] clk: samsung: add support for 145xx and 1460x PLLs Date: Tue, 02 Sep 2014 21:05:37 +0530 Message-id: <1409672143-8574-2-git-send-email-ch.naveen@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1409672143-8574-1-git-send-email-ch.naveen@samsung.com> References: <1409672143-8574-1-git-send-email-ch.naveen@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrFLMWRmVeSWpSXmKPExsWyRsSkSlfrKWuIwcQPbBbvl/UwWsw/co7V onfBVTaLTY+vsVrMOL+PyeLphItsFou2/We2+L9nB7vF+hmvWRw4PdbMW8PosXPWXXaPTas6 2TzuXNvD5rF5Sb1H35ZVjB6fN8kFsEdx2aSk5mSWpRbp2yVwZSxY95qx4LRsRcupb2wNjKsk uhg5OCQETCQuHKnpYuQEMsUkLtxbz9bFyMUhJLCUUeJp5yI2iISJROfTq4wQiUWMEneWz2eF cPqZJJbMXMYKUsUmYCZxcNFqdhBbREBDYkrXY3aQImaBB4wSjceusIAkhAW8JBbcXsIIsppF QFXiwIJAEJNXwEVi4v5YiIMUJOZMsgEp5hRwlVjyYBsbSFgIqOLEKXOIc3axS1x8ZgFiswgI SHybfIgFolNWYtMBZogSSYmDK26wTGAUXsDIsIpRNLUguaA4Kb3IRK84Mbe4NC9dLzk/dxMj MApO/3s2YQfjvQPWhxgFOBiVeHglfrCECLEmlhVX5h5iNAXaMJFZSjQ5HxhreSXxhsZmRham JqbGRuaWZkrivK+lfgYLCaQnlqRmp6YWpBbFF5XmpBYfYmTi4JRqYFyau+pgTfv0yjPPPhgb 7xbZbaOySun4JXeN7IkPr335IB2quTx76Z0fLEnulo1Kq4IsrFwy+ydO7Nn7q+zPfqFZUh9L TJyfZDZeqPgznf3q7KdbU3Mr56a1/b1eL8S3/82mHJ6l+64f8Lv7IeBxdtO95l0Tzd8zedyR tPjGpHjM5ofvB3ntB9xKLMUZiYZazEXFiQA9oHFifQIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGIsWRmVeSWpSXmKPExsVy+t9jAV3Np6whBr0vrSzeL+thtJh/5Byr Re+Cq2wWmx5fY7WYcX4fk8XTCRfZLBZt+89s8X/PDnaL9TNeszhweqyZt4bRY+esu+wem1Z1 snncubaHzWPzknqPvi2rGD0+b5ILYI9qYLTJSE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1 tLQwV1LIS8xNtVVy8QnQdcvMATpNSaEsMacUKBSQWFyspG+HaUJoiJuuBUxjhK5vSBBcj5EB GkhYw5ixYN1rxoLTshUtp76xNTCukuhi5OSQEDCR6Hx6lRHCFpO4cG89WxcjF4eQwCJGiTvL 57NCOP1MEktmLmMFqWITMJM4uGg1O4gtIqAhMaXrMTtIEbPAA0aJxmNXWEASwgJeEgtuLwEa y8HBIqAqcWBBIIjJK+AiMXF/LIgpIaAgMWeSDUgxp4CrxJIH29hAwkJAFSdOmU9g5F3AyLCK UTS1ILmgOCk911CvODG3uDQvXS85P3cTIzjOnkntYFzZYHGIUYCDUYmHV/IHS4gQa2JZcWXu IUYJDmYlEd6CR6whQrwpiZVVqUX58UWlOanFhxhNgS6ayCwlmpwPTAF5JfGGxibmpsamliYW JmaWSuK8B1qtA4UE0hNLUrNTUwtSi2D6mDg4pRoYM2858srf/yaTESHbmvLXdtaN5wnZpaGf pi7P5I0ukXiVeSTiwdMS720LmG5ebuhYvS6bY/+x/XMiP2u+PWm+aMfal8t5/25oT1C3TMn3 4ZT1ehnUeoI5a+lRy6ylBTX3Oat07n/zEJTj9rv9V1JjZkuqSWHOeXv3vOvPKjQ/fdrVfs1L U+26EktxRqKhFnNRcSIATYFKbskCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PLL145xx is similar to PLL35xx and PLL1460x is almost similar to PLL46xx with minor differences in bit positions. Hence, reuse the functions defined for pll_35xx and pll_46xx to support 145xx and 1460x PLLs respectively. Signed-off-by: Naveen Krishna Chatradhi Cc: Tomasz Figa Cc: Mike Turquette --- drivers/clk/samsung/clk-pll.c | 25 ++++++++++++++++++++----- drivers/clk/samsung/clk-pll.h | 4 ++++ 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b07fad2..9d70e5c 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = { #define PLL46XX_VSEL_MASK (1) #define PLL46XX_MDIV_MASK (0x1FF) +#define PLL1460X_MDIV_MASK (0x3FF) + #define PLL46XX_PDIV_MASK (0x3F) #define PLL46XX_SDIV_MASK (0x7) #define PLL46XX_VSEL_SHIFT (27) @@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, pll_con0 = __raw_readl(pll->con_reg); pll_con1 = __raw_readl(pll->con_reg + 4); - mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; + mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? + PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : pll_con1 & PLL46XX_KDIV_MASK; - shift = pll->type == pll_4600 ? 16 : 10; + shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; + fvco *= (mdiv << shift) + kdiv; do_div(fvco, (pdiv << sdiv)); fvco >>= shift; @@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, lock = 0xffff; /* Set PLL PMS and VSEL values. */ - con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + if (pll->type == pll_1460x) { + con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | + (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT)); + } else { + con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) | (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT)); + con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; + } + con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | (rate->pdiv << PLL46XX_PDIV_SHIFT) | - (rate->sdiv << PLL46XX_SDIV_SHIFT) | - (rate->vsel << PLL46XX_VSEL_SHIFT); + (rate->sdiv << PLL46XX_SDIV_SHIFT); /* Set PLL K, MFR and MRR values. */ con1 = __raw_readl(pll->con_reg + 0x4); @@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, /* clk_ops for 35xx and 2550 are similar */ case pll_35xx: case pll_2550: + case pll_1450x: + case pll_1451x: + case pll_1452x: if (!pll->rate_table) init.ops = &samsung_pll35xx_clk_min_ops; else @@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_4600: case pll_4650: case pll_4650c: + case pll_1460x: if (!pll->rate_table) init.ops = &samsung_pll46xx_clk_min_ops; else diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index c0ed4d4..213de9a 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -33,6 +33,10 @@ enum samsung_pll_type { pll_s3c2440_mpll, pll_2550xx, pll_2650xx, + pll_1450x, + pll_1451x, + pll_1452x, + pll_1460x, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \