From patchwork Fri Sep 5 12:34:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 4851861 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 783D0C0338 for ; Fri, 5 Sep 2014 12:36:06 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B317B20109 for ; Fri, 5 Sep 2014 12:36:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ED37620225 for ; Fri, 5 Sep 2014 12:35:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932175AbaIEMfM (ORCPT ); Fri, 5 Sep 2014 08:35:12 -0400 Received: from mailout1.w1.samsung.com ([210.118.77.11]:23866 "EHLO mailout1.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751676AbaIEMfK (ORCPT ); Fri, 5 Sep 2014 08:35:10 -0400 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout1.w1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NBF001E1HRF3X80@mailout1.w1.samsung.com>; Fri, 05 Sep 2014 13:38:03 +0100 (BST) X-AuditID: cbfec7f5-b7f776d000003e54-10-5409adfce22d Received: from eusync2.samsung.com ( [203.254.199.212]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id E1.C6.15956.CFDA9045; Fri, 05 Sep 2014 13:35:08 +0100 (BST) Received: from AMDC1943.digital.local ([106.116.151.171]) by eusync2.samsung.com (Oracle Communications Messaging Server 7u4-23.01(7.0.4.23.0) 64bit (built Aug 10 2011)) with ESMTPA id <0NBF00A35HMCTZ80@eusync2.samsung.com>; Fri, 05 Sep 2014 13:35:08 +0100 (BST) From: Krzysztof Kozlowski To: Russell King , Kukjin Kim , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Kyungmin Park , Marek Szyprowski , Bartlomiej Zolnierkiewicz , Tomasz Figa , Daniel Lezcano , Sachin Kamat , Krzysztof Kozlowski Subject: [PATCH v5 RESEND 3/3] ARM: exynos4: hotplug: Fix CPU idle clock down after CPU off Date: Fri, 05 Sep 2014 14:34:55 +0200 Message-id: <1409920495-16533-3-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1409920495-16533-1-git-send-email-k.kozlowski@samsung.com> References: <1409920495-16533-1-git-send-email-k.kozlowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprELMWRmVeSWpSXmKPExsVy+t/xK7p/1nKGGJz8K26xccZ6Vot5n2Ut Xr8wtOhdcJXN4mzTG3aLTY+vsVpc3jWHzWLG+X1MFrcv81qsPXKX3eLkn15Gi1W7/jA68Hi0 NPeweeycdZfd4861PWwem5fUe/RtWcXo8XmTXABbFJdNSmpOZllqkb5dAlfGjo6D7AUnNCt+ T7jG2sD4Q7GLkZNDQsBE4uns2cwQtpjEhXvr2boYuTiEBJYySuzrOcsM4fQxSSzafwKsik3A WGLz8iVgVSICOxgllt+7zA7iMAscYZJYdmIzE0iVsECsxOsZt9hAbBYBVYmF/9awgti8Au4S a/qfskHsk5M4eWwyWJxTwEPib0czC4gtBFQz+d065gmMvAsYGVYxiqaWJhcUJ6XnGukVJ+YW l+al6yXn525ihITj1x2MS49ZHWIU4GBU4uHt0OQMEWJNLCuuzD3EKMHBrCTC6z4FKMSbklhZ lVqUH19UmpNafIiRiYNTqoFx4m2zcx/n75Zh2H8w92/ydLtJuS3P/CSu/cldMZd7H+el3y/c aw46XD5lv8eotGVf+jspR4fX2U4KCp5M9213SQVs+PUwT67t13zJ2qvRPpHK80xFZ53kK5bL 7TrxOvVxl1GRfomcyMoNnxU1JgnuVXzdffruu3+PufUuftTRfnT58Mw5b15UK7EUZyQaajEX FScCAM56yG4lAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-8.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Exynos4 USE_DELAYED_RESET_ASSERTION must be set in ARM_COREx_OPTION register during CPU power down. This is the proper way of powering down CPU on Exynos4. Additionally on Exynos4212 without this the CPU clock down feature won't work after powering down some CPU and the online CPUs will work at full frequency chosen by CPUfreq governor. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Tomasz Figa --- Changes since v4: 1. Rebase on linux-next-20140804. 2. Add Reviewed-by Tomasz Figa. Changes since v3: 1. Add patches moving hotplug code to platsmp.c file (patches 1 and 2). Suggested by Tomasz Figa. 2. Remove declaration of exynos_clear_delayed_reset_assertion() in header because hotplug code is integrated into platsmp.c file. Suggested by Tomasz Figa. 3. Replace 'clear' helper with 'set' helper. Suggested by Tomasz Figa. Changes since v2: 1. Add missing disable of the "use delayed reset assertion" feature when starting secondary CPU (suggested by Tomasz Figa). Changes since v1: 1. Use delayed reset assertion on all Exynos4 family and all cores, not only on core 1 of Exynos4212. 2. Rebase on Tomasz Figa's patch: ARM: EXYNOS: Fix core ID used by platsmp and hotplug code http://www.spinics.net/lists/linux-samsung-soc/msg31604.html Tomasz's patch is currently applied to Kukjin's v3.16-samsung-fixes-4 --- arch/arm/mach-exynos/platsmp.c | 43 +++++++++++++++++++++++++++++++++++++++-- arch/arm/mach-exynos/regs-pmu.h | 3 +++ 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 83b20a38a598..99c151bf30ad 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -34,8 +34,32 @@ extern void exynos4_secondary_startup(void); +/* + * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs + * during hot-(un)plugging CPUx. + * + * The feature can be cleared safely during first boot of secondary CPU. + * + * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering + * down a CPU so the CPU idle clock down feature could properly detect global + * idle state when CPUx is off. + */ +static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable) +{ + if (soc_is_exynos4()) { + unsigned int tmp; + + tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id)); + if (enable) + tmp |= S5P_USE_DELAYED_RESET_ASSERTION; + else + tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION); + pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id)); + } +} + #ifdef CONFIG_HOTPLUG_CPU -static inline void cpu_leave_lowpower(void) +static inline void cpu_leave_lowpower(u32 core_id) { unsigned int v; @@ -49,6 +73,8 @@ static inline void cpu_leave_lowpower(void) : "=&r" (v) : "Ir" (CR_C), "Ir" (0x40) : "cc"); + + exynos_set_delayed_reset_assertion(core_id, false); } static inline void platform_do_lowpower(unsigned int cpu, int *spurious) @@ -61,6 +87,14 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious) /* Turn the CPU off on next WFI instruction. */ exynos_cpu_power_down(core_id); + /* + * Exynos4 SoCs require setting + * USE_DELAYED_RESET_ASSERTION so the CPU idle + * clock down feature could properly detect + * global idle state when CPUx is off. + */ + exynos_set_delayed_reset_assertion(core_id, true); + wfi(); if (pen_release == core_id) { @@ -286,6 +320,9 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) udelay(10); } + /* No harm if this is called during first boot of secondary CPU */ + exynos_set_delayed_reset_assertion(core_id, false); + /* * now the secondary core is starting up let it run its * calibrations, then wait for it to finish @@ -376,6 +413,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus) static void exynos_cpu_die(unsigned int cpu) { int spurious = 0; + u32 mpidr = cpu_logical_map(cpu); + u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); v7_exit_coherency_flush(louis); @@ -385,7 +424,7 @@ static void exynos_cpu_die(unsigned int cpu) * bring this CPU back into the world of cache * coherency, and then restore interrupts */ - cpu_leave_lowpower(); + cpu_leave_lowpower(core_id); if (spurious) pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 96a1569262b5..4e9b4440e2bd 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -20,6 +20,7 @@ #define S5P_USE_STANDBY_WFI0 (1 << 16) #define S5P_USE_STANDBY_WFE0 (1 << 24) +#define S5P_USE_DELAYED_RESET_ASSERTION BIT(12) #define EXYNOS_SWRESET 0x0400 #define EXYNOS5440_SWRESET 0x00C4 @@ -106,6 +107,8 @@ (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) #define EXYNOS_ARM_CORE_STATUS(_nr) \ (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) +#define EXYNOS_ARM_CORE_OPTION(_nr) \ + (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x8) #define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500 #define EXYNOS_COMMON_CONFIGURATION(_nr) \