From patchwork Wed Sep 10 16:37:34 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 4879181 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D510CC0338 for ; Wed, 10 Sep 2014 16:37:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A23C7201C7 for ; Wed, 10 Sep 2014 16:37:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DB70F201B9 for ; Wed, 10 Sep 2014 16:37:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751523AbaIJQhu (ORCPT ); Wed, 10 Sep 2014 12:37:50 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:60787 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751472AbaIJQht (ORCPT ); Wed, 10 Sep 2014 12:37:49 -0400 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NBP00E3D270TK70@mailout2.samsung.com> for linux-samsung-soc@vger.kernel.org; Thu, 11 Sep 2014 01:37:48 +0900 (KST) X-AuditID: cbfee61a-f79e46d00000134f-2d-54107e5b1ebe Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 0B.38.04943.B5E70145; Thu, 11 Sep 2014 01:37:48 +0900 (KST) Received: from amdc1344.digital.local ([106.116.147.32]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NBP00MR226PZG40@mmp2.samsung.com>; Thu, 11 Sep 2014 01:37:47 +0900 (KST) From: Sylwester Nawrocki To: kgene.kim@samsung.com Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, m.szyprowski@samsung.com, Sylwester Nawrocki Subject: [PATCH] ARM: dts: Specify default clocks for Exynos4 FIMC devices Date: Wed, 10 Sep 2014 18:37:34 +0200 Message-id: <1410367054-30926-1-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrKJMWRmVeSWpSXmKPExsVy+t9jQd2YOoEQgz2n2Cx6F1xls9j0+Bqr xYzz+5gs1h65y25x+E07qwOrx+Yl9R59W1YxenzeJBfAHMVlk5Kak1mWWqRvl8CVMXfjQfaC 3dIVb1fNYG1gbBXrYuTgkBAwkZi3MLOLkRPIFJO4cG89WxcjF4eQwHRGia1777JAOB1MEu/O drCAVLEJGEr0Hu1jBLFFBCQlmhr+MIMUMQtMYZR4dvQsO0hCWMBL4m7bTXaQDSwCqhJN3dIg YV4BN4nbB16yQCxWkJgzyWYCI/cCRoZVjKKpBckFxUnpuYZ6xYm5xaV56XrJ+bmbGMGefya1 g3Flg8UhRgEORiUeXoFa/hAh1sSy4srcQ4wSHMxKIrxNDgIhQrwpiZVVqUX58UWlOanFhxil OViUxHkPtFoHCgmkJ5akZqemFqQWwWSZODilGhh5p+3MPzjXrnR7N8exDTKf1rk1vZKZ4/iV 53t170NPnpOzuF7eqF/AMH/rvy0tmR/XvnPe8nVWc0Or10KBrycK2/mqNZV7G6c+42+re5Vh pvi/Y8qOw2XX9cy8HE3MToWrJ14TF756ZL2InEz1Vh0d9muau6yrDQTTyhXitdLfthRtC3g/ Y4cSS3FGoqEWc1FxIgAiGaT4+AEAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The default mux and divider clocks are specified in device tree so that the FIMC devices in Exynos4210 and Exynos4x12 SoCs are clocked from recommended clock source and with maximum supported frequency. If needed these settings could be overrode in board specific dts files, however they are in practice optimal in most cases. Signed-off-by: Sylwester Nawrocki --- arch/arm/boot/dts/exynos4210.dtsi | 16 ++++++++++++++++ arch/arm/boot/dts/exynos4x12.dtsi | 16 ++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 807bb5b..0969d2e 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -154,18 +154,30 @@ samsung,pix-limits = <4224 8192 1920 4224>; samsung,mainscaler-ext; samsung,cam-if; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_1: fimc@11810000 { samsung,pix-limits = <4224 8192 1920 4224>; samsung,mainscaler-ext; samsung,cam-if; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_2: fimc@11820000 { samsung,pix-limits = <4224 8192 1920 4224>; samsung,mainscaler-ext; samsung,lcd-wb; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_3: fimc@11830000 { @@ -173,6 +185,10 @@ samsung,rotators = <0>; samsung,mainscaler-ext; samsung,lcd-wb; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 861bb91..38ba14f 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -162,6 +162,10 @@ samsung,mainscaler-ext; samsung,isp-wb; samsung,cam-if; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_1: fimc@11810000 { @@ -170,6 +174,10 @@ samsung,mainscaler-ext; samsung,isp-wb; samsung,cam-if; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_2: fimc@11820000 { @@ -179,6 +187,10 @@ samsung,isp-wb; samsung,lcd-wb; samsung,cam-if; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_3: fimc@11830000 { @@ -188,6 +200,10 @@ samsung,mainscaler-ext; samsung,isp-wb; samsung,lcd-wb; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_lite_0: fimc-lite@12390000 {