From patchwork Thu Sep 11 10:20:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 4884441 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 0E4B19F32F for ; Thu, 11 Sep 2014 10:25:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B15642022D for ; Thu, 11 Sep 2014 10:25:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CC4AE2011E for ; Thu, 11 Sep 2014 10:25:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754335AbaIKKZu (ORCPT ); Thu, 11 Sep 2014 06:25:50 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:43695 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754328AbaIKKZs (ORCPT ); Thu, 11 Sep 2014 06:25:48 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NBQ0083IFMZQ170@mailout3.samsung.com>; Thu, 11 Sep 2014 19:25:47 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.126]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 5D.0B.04467.BA871145; Thu, 11 Sep 2014 19:25:47 +0900 (KST) X-AuditID: cbfee68f-f797f6d000001173-d7-541178ab0a2c Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 33.64.04943.BA871145; Thu, 11 Sep 2014 19:25:47 +0900 (KST) Received: from chnaveen-ubuntu.sisodomain.com ([107.108.83.161]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NBQ00IEPFMF1D80@mmp1.samsung.com>; Thu, 11 Sep 2014 19:25:46 +0900 (KST) From: Naveen Krishna Chatradhi To: linux-arm-kernel@lists.infradead.org Cc: naveenkrishna.ch@gmail.com, linux-samsung-soc@vger.kernel.org, catalin.marinas@arm.com, robh@kernel.org, devicetree@vger.kernel.org, tomasz.figa@gmail.com, kgene.kim@samsung.com, Mike Turquette Subject: [PATCH v3 1/8] clk: samsung: add support for 145xx and 1460x PLLs Date: Thu, 11 Sep 2014 15:50:45 +0530 Message-id: <1410430852-3491-2-git-send-email-ch.naveen@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1410430852-3491-1-git-send-email-ch.naveen@samsung.com> References: <1410430852-3491-1-git-send-email-ch.naveen@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNLMWRmVeSWpSXmKPExsWyRsSkTnd1hWCIwZXVghbvl/UwWsw/co7V onfBVTaLTY+vsVrMOL+PyeLphItsFou2/We2+L9nB7vFql1/GB04PdbMW8PosXPWXXaPTas6 2TzuXNvD5rF5Sb1H35ZVjB6fN8kFsEdx2aSk5mSWpRbp2yVwZXw6P5et4JxsxfsWsQbGtRJd jJwcEgImEh1NK1kgbDGJC/fWs4HYQgJLGSXWHPPpYuQAq7l1X7+LkQsovIhR4sqURywQTj+T xK9bHxhBGtgEzCQOLlrNDmKLCGhITOl6zA5SxCzwmFHiW8tOsCJhAS+J19vvsIBMZRFQlWhb yAsS5hVwkZjwo50RYpmCxJxJNiBhTgFXif9/17JC3OMi0fh2FhvISAmBXewS+7f+BDuaRUBA 4tvkQywQvbISmw4wQ/wiKXFwxQ2WCYzCCxgZVjGKphYkFxQnpRcZ6xUn5haX5qXrJefnbmIE xsHpf8/6dzDePWB9iFGAg1GJh7eCRTBEiDWxrLgy9xCjKdCGicxSosn5wGjLK4k3NDYzsjA1 MTU2Mrc0UxLnXSj1M1hIID2xJDU7NbUgtSi+qDQntfgQIxMHp1QDY2ZaY5HpGw7O8yvZZiTc 3tsk5RVyRqxqQnKN3czbSzOU2u9m1M74vkbCWm+954HyHWfygz6GlM6v77Wa4CmwwGnm3TCh 9ReXfEs1dC6q+ijO3bUn8/H9+xwncxw/71rwxjDHivkSj0Sjq2vz7hqnVBGeS7VOdclHX9k/ m2lgF6wSFKvb/bVfiaU4I9FQi7moOBEAkVmxuX4CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrGIsWRmVeSWpSXmKPExsVy+t9jAd3VFYIhBj/mcli8X9bDaDH/yDlW i94FV9ksNj2+xmox4/w+JounEy6yWSza9p/Z4v+eHewWq3b9YXTg9Fgzbw2jx85Zd9k9Nq3q ZPO4c20Pm8fmJfUefVtWMXp83iQXwB7VwGiTkZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhr aGlhrqSQl5ibaqvk4hOg65aZA3SakkJZYk4pUCggsbhYSd8O04TQEDddC5jGCF3fkCC4HiMD NJCwhjHj0/m5bAXnZCvet4g1MK6V6GLk4JAQMJG4dV+/i5ETyBSTuHBvPVsXIxeHkMAiRokr Ux6xQDj9TBK/bn1gBKliEzCTOLhoNTuILSKgITGl6zE7SBGzwGNGiW8tO8GKhAW8JF5vv8MC soFFQFWibSEvSJhXwEViwo92RojFChJzJtmAhDkFXCX+/13LCmILAZU0vp3FNoGRdwEjwypG 0dSC5ILipPRcQ73ixNzi0rx0veT83E2M4Dh7JrWDcWWDxSFGAQ5GJR7eChbBECHWxLLiytxD jBIczEoivKWFQCHelMTKqtSi/Pii0pzU4kOMpkA3TWSWEk3OB6aAvJJ4Q2MTc1NjU0sTCxMz SyVx3gOt1oFCAumJJanZqakFqUUwfUwcnFINjAdPfTjeuOfT67lGOjm18QnP56ROaLkcYffl fIuhn+y2JQq+f137Lu1anNP45OL0Ww9PadWo+PnGtf6bO6l+wr/dczl/Zk6w2PxO9mXVSt6f L/xWirabHvb488e8uOOkXvemv9IPd1zeHROdLf7NwzTin2vY12fHDx/VfvPkg83WQ0+C+zkr 3gkqsRRnJBpqMRcVJwIAsqkl2skCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PLL145xx is similar to PLL35xx and PLL1460x is almost similar to PLL46xx with minor differences in bit positions. Hence, reuse the functions defined for pll_35xx and pll_46xx to support 145xx and 1460x PLLs respectively. Signed-off-by: Naveen Krishna Chatradhi Cc: Tomasz Figa Cc: Mike Turquette --- drivers/clk/samsung/clk-pll.c | 25 ++++++++++++++++++++----- drivers/clk/samsung/clk-pll.h | 4 ++++ 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b07fad2..9d70e5c 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = { #define PLL46XX_VSEL_MASK (1) #define PLL46XX_MDIV_MASK (0x1FF) +#define PLL1460X_MDIV_MASK (0x3FF) + #define PLL46XX_PDIV_MASK (0x3F) #define PLL46XX_SDIV_MASK (0x7) #define PLL46XX_VSEL_SHIFT (27) @@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, pll_con0 = __raw_readl(pll->con_reg); pll_con1 = __raw_readl(pll->con_reg + 4); - mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; + mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? + PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : pll_con1 & PLL46XX_KDIV_MASK; - shift = pll->type == pll_4600 ? 16 : 10; + shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; + fvco *= (mdiv << shift) + kdiv; do_div(fvco, (pdiv << sdiv)); fvco >>= shift; @@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, lock = 0xffff; /* Set PLL PMS and VSEL values. */ - con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + if (pll->type == pll_1460x) { + con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | + (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT)); + } else { + con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) | (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT)); + con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; + } + con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | (rate->pdiv << PLL46XX_PDIV_SHIFT) | - (rate->sdiv << PLL46XX_SDIV_SHIFT) | - (rate->vsel << PLL46XX_VSEL_SHIFT); + (rate->sdiv << PLL46XX_SDIV_SHIFT); /* Set PLL K, MFR and MRR values. */ con1 = __raw_readl(pll->con_reg + 0x4); @@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, /* clk_ops for 35xx and 2550 are similar */ case pll_35xx: case pll_2550: + case pll_1450x: + case pll_1451x: + case pll_1452x: if (!pll->rate_table) init.ops = &samsung_pll35xx_clk_min_ops; else @@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_4600: case pll_4650: case pll_4650c: + case pll_1460x: if (!pll->rate_table) init.ops = &samsung_pll46xx_clk_min_ops; else diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index c0ed4d4..213de9a 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -33,6 +33,10 @@ enum samsung_pll_type { pll_s3c2440_mpll, pll_2550xx, pll_2650xx, + pll_1450x, + pll_1451x, + pll_1452x, + pll_1460x, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \