From patchwork Fri Sep 12 15:26:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naveen Krishna Chatradhi X-Patchwork-Id: 4895971 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 53E499F430 for ; Fri, 12 Sep 2014 15:27:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 53F722017A for ; Fri, 12 Sep 2014 15:32:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 84D15202B8 for ; Fri, 12 Sep 2014 15:32:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751345AbaILPci (ORCPT ); Fri, 12 Sep 2014 11:32:38 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:57619 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751296AbaILPch (ORCPT ); Fri, 12 Sep 2014 11:32:37 -0400 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NBS00IR8OIBFY60@mailout1.samsung.com>; Sat, 13 Sep 2014 00:32:35 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.123]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 0B.D0.04467.31213145; Sat, 13 Sep 2014 00:32:35 +0900 (KST) X-AuditID: cbfee68f-f797f6d000001173-ee-541312132ae4 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id E1.3D.05196.31213145; Sat, 13 Sep 2014 00:32:35 +0900 (KST) Received: from chnaveen-ubuntu.sisodomain.com ([107.108.83.161]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NBS00BEMOFWGJ70@mmp1.samsung.com>; Sat, 13 Sep 2014 00:32:35 +0900 (KST) From: Naveen Krishna Chatradhi To: linux-arm-kernel@lists.infradead.org Cc: naveenkrishna.ch@gmail.com, linux-samsung-soc@vger.kernel.org, catalin.marinas@arm.com, robh@kernel.org, devicetree@vger.kernel.org, tomasz.figa@gmail.com, kgene.kim@samsung.com, gregkh@linuxfoundation.org, Mike Turquette Subject: [PATCH v4 1/8] clk: samsung: add support for 145xx and 1460x PLLs Date: Fri, 12 Sep 2014 20:56:25 +0530 Message-id: <1410535592-5782-3-git-send-email-ch.naveen@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1410535592-5782-1-git-send-email-ch.naveen@samsung.com> References: <1410535592-5782-1-git-send-email-ch.naveen@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKLMWRmVeSWpSXmKPExsWyRsSkWldYSDjEYG6/isX7ZT2MFvOPnGO1 aF68ns2id8FVNotNj6+xWsw4v4/J4umEi2wWi7b9Z7b4v2cHu8WqXX8YHbg81sxbw+ixc9Zd do9NqzrZPO5c28PmsX/uGnaPzUvqPfq2rGL0+LxJLoAjissmJTUnsyy1SN8ugSvj0/m5bAXn ZCvet4g1MK6V6GLk5JAQMJHY/34OK4QtJnHh3nq2LkYuDiGBpYwShx9dYIcp+va6nR0isYhR 4uimJkYIp59J4mHfdSaQKjYBM4mDi1aDdYgIaEhM6XoM1sEs8J9R4tiEvcxdjBwcwgJeEtde yoHUsAioSqy+NYMNJMwr4CIx/VI+iCkhoCAxZ5INSAWngKvE+51X2EHCQkAVS2+KgwyUEDjG LtH+6AE7xBQBiW+TD7FAtMpKbDrADHGypMTBFTdYJjAKL2BkWMUomlqQXFCclF5krFecmFtc mpeul5yfu4kRGBun/z3r38F494D1IUYBDkYlHt4KFsEQIdbEsuLK3EOMpkAbJjJLiSbnAyMw ryTe0NjMyMLUxNTYyNzSTEmcd6HUz2AhgfTEktTs1NSC1KL4otKc1OJDjEwcnFINjCsbNSyu vpTgivKXfFKp9Uhg+aL3AvlfXT+fyrzefyMjOy96U6aDDt/EsOwf5mu0JyurOAlliMV06Pa9 WeG3Z/O0yoKV/1u+a7g8eSm2MO9K3JaMxjizY6ufyvEx9BlGh8hMr1z2VvBygLatmp6HoOFW L6NFciccPfLOGbhsF4hVzGbOue6kxFKckWioxVxUnAgAhxRmHIgCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrPIsWRmVeSWpSXmKPExsVy+t9jAV1hIeEQg22bpC3eL+thtJh/5Byr RfPi9WwWvQuusllsenyN1WLG+X1MFk8nXGSzWLTtP7PF/z072C1W7frD6MDlsWbeGkaPnbPu sntsWtXJ5nHn2h42j/1z17B7bF5S79G3ZRWjx+dNcgEcUQ2MNhmpiSmpRQqpecn5KZl56bZK 3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlARyoplCXmlAKFAhKLi5X07TBNCA1x07WA aYzQ9Q0JgusxMkADCWsYMz6dn8tWcE624n2LWAPjWokuRk4OCQETiW+v29khbDGJC/fWs3Ux cnEICSxilDi6qYkRwulnknjYd50JpIpNwEzi4KLVYB0iAhoSU7oes4MUMQv8Z5Q4NmEvcxcj B4ewgJfEtZdyIDUsAqoSq2/NYAMJ8wq4SEy/lA9iSggoSMyZZANSwSngKvF+5xV2kLAQUMXS m+ITGHkXMDKsYhRNLUguKE5KzzXSK07MLS7NS9dLzs/dxAiOvGfSOxhXNVgcYhTgYFTi4a1k EQwRYk0sK67MPcQowcGsJMJ745VQiBBvSmJlVWpRfnxRaU5q8SFGU6CTJjJLiSbnA5NCXkm8 obGJuamxqaWJhYmZpZI478FW60AhgfTEktTs1NSC1CKYPiYOTqkGxp4Nq00jy7ynhth/NLKt 03NavdRMdrdMs3HZxwvPxL/9X7rC0GcVh+1bq91mlVot0uovbF7YdVy7JZi6nfW2uJyoxQmj /7XC38U99vDrCgrbTsnP+WN8/MSpeLWT+01bSgJ95cVuBdpu+3BHYI9le3KsUba/dXf+/5z2 PY8CQqP/5PKsOeWuxFKckWioxVxUnAgAIjyaudICAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-9.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PLL145xx is similar to PLL35xx and PLL1460x is almost similar to PLL46xx with minor differences in bit positions. Hence, reuse the functions defined for pll_35xx and pll_46xx to support 145xx and 1460x PLLs respectively. Signed-off-by: Naveen Krishna Chatradhi Cc: Tomasz Figa Cc: Mike Turquette --- drivers/clk/samsung/clk-pll.c | 25 ++++++++++++++++++++----- drivers/clk/samsung/clk-pll.h | 4 ++++ 2 files changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index b07fad2..9d70e5c 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -482,6 +482,8 @@ static const struct clk_ops samsung_pll45xx_clk_min_ops = { #define PLL46XX_VSEL_MASK (1) #define PLL46XX_MDIV_MASK (0x1FF) +#define PLL1460X_MDIV_MASK (0x3FF) + #define PLL46XX_PDIV_MASK (0x3F) #define PLL46XX_SDIV_MASK (0x7) #define PLL46XX_VSEL_SHIFT (27) @@ -511,13 +513,15 @@ static unsigned long samsung_pll46xx_recalc_rate(struct clk_hw *hw, pll_con0 = __raw_readl(pll->con_reg); pll_con1 = __raw_readl(pll->con_reg + 4); - mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; + mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? + PLL1460X_MDIV_MASK : PLL46XX_MDIV_MASK); pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; kdiv = pll->type == pll_4650c ? pll_con1 & PLL4650C_KDIV_MASK : pll_con1 & PLL46XX_KDIV_MASK; - shift = pll->type == pll_4600 ? 16 : 10; + shift = ((pll->type == pll_4600) || (pll->type == pll_1460x)) ? 16 : 10; + fvco *= (mdiv << shift) + kdiv; do_div(fvco, (pdiv << sdiv)); fvco >>= shift; @@ -573,14 +577,21 @@ static int samsung_pll46xx_set_rate(struct clk_hw *hw, unsigned long drate, lock = 0xffff; /* Set PLL PMS and VSEL values. */ - con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + if (pll->type == pll_1460x) { + con0 &= ~((PLL1460X_MDIV_MASK << PLL46XX_MDIV_SHIFT) | + (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | + (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT)); + } else { + con0 &= ~((PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT) | (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT) | (PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT) | (PLL46XX_VSEL_MASK << PLL46XX_VSEL_SHIFT)); + con0 |= rate->vsel << PLL46XX_VSEL_SHIFT; + } + con0 |= (rate->mdiv << PLL46XX_MDIV_SHIFT) | (rate->pdiv << PLL46XX_PDIV_SHIFT) | - (rate->sdiv << PLL46XX_SDIV_SHIFT) | - (rate->vsel << PLL46XX_VSEL_SHIFT); + (rate->sdiv << PLL46XX_SDIV_SHIFT); /* Set PLL K, MFR and MRR values. */ con1 = __raw_readl(pll->con_reg + 0x4); @@ -1190,6 +1201,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, /* clk_ops for 35xx and 2550 are similar */ case pll_35xx: case pll_2550: + case pll_1450x: + case pll_1451x: + case pll_1452x: if (!pll->rate_table) init.ops = &samsung_pll35xx_clk_min_ops; else @@ -1223,6 +1237,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, case pll_4600: case pll_4650: case pll_4650c: + case pll_1460x: if (!pll->rate_table) init.ops = &samsung_pll46xx_clk_min_ops; else diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index c0ed4d4..213de9a 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -33,6 +33,10 @@ enum samsung_pll_type { pll_s3c2440_mpll, pll_2550xx, pll_2650xx, + pll_1450x, + pll_1451x, + pll_1452x, + pll_1460x, }; #define PLL_35XX_RATE(_rate, _m, _p, _s) \