From patchwork Thu Nov 20 16:14:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 5349281 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6FE49C11AC for ; Thu, 20 Nov 2014 16:15:21 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 82AF820221 for ; Thu, 20 Nov 2014 16:15:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5E4CC201B9 for ; Thu, 20 Nov 2014 16:15:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756742AbaKTQPO (ORCPT ); Thu, 20 Nov 2014 11:15:14 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:31451 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755212AbaKTQPN (ORCPT ); Thu, 20 Nov 2014 11:15:13 -0500 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NFC00D6TIHBL600@mailout4.samsung.com> for linux-samsung-soc@vger.kernel.org; Fri, 21 Nov 2014 01:15:11 +0900 (KST) X-AuditID: cbfee61a-f79c06d000004e71-e2-546e138f4470 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 30.3D.20081.F831E645; Fri, 21 Nov 2014 01:15:11 +0900 (KST) Received: from amdc1344.digital.local ([106.116.147.32]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NFC00K6WIH20M80@mmp1.samsung.com>; Fri, 21 Nov 2014 01:15:11 +0900 (KST) From: Sylwester Nawrocki To: kgene@kernel.org Cc: drake@endlessm.com, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, Sylwester Nawrocki Subject: [PATCH] ARM: dts: Specify default clocks for Exynos4 camera devices Date: Thu, 20 Nov 2014 17:14:59 +0100 Message-id: <1416500099-19656-1-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.7.9.5 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMJMWRmVeSWpSXmKPExsVy+t9jAd1+4bwQg9YHYhaP5j9mtuhdcJXN ov/xa2aLTY+vsVrMOL+PyeLwm3ZWBzaPRd+zPDat6mTz2Lyk3qNvyypGj8+b5AJYo7hsUlJz MstSi/TtErgyTm/vYyxYbFaxfvln1gbGbdpdjJwcEgImEksajjFD2GISF+6tZ+ti5OIQEljE KNH36DMzhNPBJPFhz1EWkCo2AUOJ3qN9jF2MHBwiAiISsy9wgdQwCyxnlJjW8IsJpEZYwEfi w9MGMJtFQFXiQ3MbK0g9r4CbxPm71SCmhICCxJxJNhMYuRcwMqxiFE0tSC4oTkrPNdQrTswt Ls1L10vOz93ECA6KZ1I7GFc2WBxiFOBgVOLhTbDIDRFiTSwrrsw9xCjBwawkwivHnhcixJuS WFmVWpQfX1Sak1p8iFGag0VJnPfGTaBqgfTEktTs1NSC1CKYLBMHp1QDI8ti3d4Qzguqk7q4 T19RbD228MElxvP25y0Eio0WyNU+tVz/Jieh5LFR6f13j/QeXPg0I/fp41LTKvfV98KeRvlc uKxvxmWr2xGTsfr1OpG334+5Lf8sYJZ2Jkh70bXwqS3i71mWFvySX7al5maKz+OGlu1FofKi u1o3FzkdrLqftVBbQr38pxJLcUaioRZzUXEiAJLIcvAGAgAA Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Specify the default mux and divider clocks in device tree to ensure the FIMC devices on Trats, Trats2, Universal_c210 and Odroid X2/U3 boards are clocked from recommended clock source and with maximum supported frequency. For Trats2 also the MIPI-CSIS and the camera sensor clocks are configured, the 'clock-frequency' property is deprecated in favour of 'assigned-clock-rates' property. Signed-off-by: Sylwester Nawrocki --- arch/arm/boot/dts/exynos4210-trats.dts | 16 ++++++++++++ arch/arm/boot/dts/exynos4210-universal_c210.dts | 16 ++++++++++++ arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 16 ++++++++++++ arch/arm/boot/dts/exynos4412-trats2.dts | 32 ++++++++++++++++++++--- 4 files changed, 77 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index f516da9..7208362 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -431,18 +431,34 @@ fimc_0: fimc@11800000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_1: fimc@11810000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_2: fimc@11820000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_3: fimc@11830000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d50eb3a..aaf0cae 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -473,18 +473,34 @@ fimc_0: fimc@11800000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_1: fimc@11810000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_2: fimc@11820000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_3: fimc@11830000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index c697ff0..adf1331 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -82,18 +82,34 @@ fimc_0: fimc@11800000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_1: fimc@11810000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_2: fimc@11820000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_3: fimc@11830000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 8ee20bd..08bc948 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -701,28 +701,51 @@ pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; pinctrl-names = "default"; status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CAM0>, + <&clock CLK_MOUT_CAM1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>, + <&clock CLK_MOUT_MPLL_USER_T>; fimc_0: fimc@11800000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_1: fimc@11810000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_2: fimc@11820000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_3: fimc@11830000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; csis_0: csis@11880000 { status = "okay"; vddcore-supply = <&ldo8_reg>; vddio-supply = <&ldo10_reg>; - clock-frequency = <176000000>; + assigned-clocks = <&clock CLK_MOUT_CSIS0>, + <&clock CLK_SCLK_CSIS0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; /* Camera C (3) MIPI CSI-2 (CSIS0) */ port@3 { @@ -736,10 +759,13 @@ }; csis_1: csis@11890000 { + status = "okay"; vddcore-supply = <&ldo8_reg>; vddio-supply = <&ldo10_reg>; - clock-frequency = <160000000>; - status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CSIS1>, + <&clock CLK_SCLK_CSIS1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; /* Camera D (4) MIPI CSI-2 (CSIS1) */ port@4 {