@@ -100,6 +100,11 @@
reg = <0x10044040 0x20>;
};
+ pd_disp1: disp1-power-domain@100440A0 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x100440A0 0x20>;
+ };
+
clock: clock-controller@10010000 {
compatible = "samsung,exynos5250-clock";
reg = <0x10010000 0x30000>;
@@ -713,6 +718,7 @@
hdmi {
compatible = "samsung,exynos4212-hdmi";
reg = <0x14530000 0x70000>;
+ samsung,power-domain = <&pd_disp1>;
interrupts = <0 95 0>;
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
@@ -725,6 +731,7 @@
mixer {
compatible = "samsung,exynos5250-mixer";
reg = <0x14450000 0x10000>;
+ samsung,power-domain = <&pd_disp1>;
interrupts = <0 94 0>;
clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
clock-names = "mixer", "sclk_hdmi";
@@ -737,6 +744,7 @@
};
dp-controller@145B0000 {
+ samsung,power-domain = <&pd_disp1>;
clocks = <&clock CLK_DP>;
clock-names = "dp";
phys = <&dp_phy>;
@@ -744,6 +752,7 @@
};
fimd@14400000 {
+ samsung,power-domain = <&pd_disp1>;
clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
clock-names = "sclk_fimd", "fimd";
};
The patch adds domain definition and references to it in appropriate devices. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> --- arch/arm/boot/dts/exynos5250.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)