From patchwork Wed Dec 10 12:09:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Majewski X-Patchwork-Id: 5468431 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 066199F1CD for ; Wed, 10 Dec 2014 12:12:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F24982015A for ; Wed, 10 Dec 2014 12:12:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7ADCB2011D for ; Wed, 10 Dec 2014 12:12:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752193AbaLJMMC (ORCPT ); Wed, 10 Dec 2014 07:12:02 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:23022 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751927AbaLJMMB (ORCPT ); Wed, 10 Dec 2014 07:12:01 -0500 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NGD002HN8JZWV90@mailout2.samsung.com>; Wed, 10 Dec 2014 21:11:59 +0900 (KST) X-AuditID: cbfee61b-f79d76d0000024d6-ec-5488388fd41a Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 0A.E8.09430.F8838845; Wed, 10 Dec 2014 21:11:59 +0900 (KST) Received: from mcdsrvbld02.digital.local ([106.116.37.23]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NGD004CJ8GLGMG0@mmp1.samsung.com>; Wed, 10 Dec 2014 21:11:59 +0900 (KST) From: Lukasz Majewski To: Eduardo Valentin , Zhang Rui Cc: Linux PM list , "linux-samsung-soc@vger.kernel.org" , Bartlomiej Zolnierkiewicz , Lukasz Majewski , Kukjin Kim , Amit Daniel Kachhap , Abhilash Kesavan , Abhilash Kesavan , Kyungmin Park , Chanwoo Choi , Lukasz Majewski Subject: [PATCH v2 06/17] thermal: cpu_cooling: dts: Define device tree bindings for Exynos cpu cooling functionality Date: Wed, 10 Dec 2014 13:09:45 +0100 Message-id: <1418213396-743-7-git-send-email-l.majewski@samsung.com> X-Mailer: git-send-email 1.7.10.4 In-reply-to: <1418213396-743-1-git-send-email-l.majewski@samsung.com> References: <1412872737-624-1-git-send-email-l.majewski@samsung.com> <1418213396-743-1-git-send-email-l.majewski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrHLMWRmVeSWpSXmKPExsVy+t9jAd1+i44Qgyk9+haP1yxmsmi4GmKx ccZ6VovrX56zWsy/co3VYs1fJYveBVfZLM42vWG3ePOI2+LNw82MFp97jzBazDi/j8niycM+ Ngdej52z7rJ7LN7zkslj3bS3zB59W1YxenzeJBfAGsVlk5Kak1mWWqRvl8CVMf1CA1PBW8OK GdfrGhjvqHYxcnJICJhI7Nj7khnCFpO4cG89WxcjF4eQwCJGiUefFjBDOF1MEndnfGEFqWIT 0JP4fPcpE4gtIuAt8XrfdEaQImaBLhaJHSvms4EkhAXKJeZ0T2cBsVkEVCUmPDkBZHNw8Aq4 SPS3RkNsU5TofjYBrJxTwFXizKkbYDOFBOolFi1+wzqBkXcBI8MqRtHUguSC4qT0XCO94sTc 4tK8dL3k/NxNjOBQfCa9g3FVg8UhRgEORiUe3oDL7SFCrIllxZW5hxglOJiVRHjfSHaECPGm JFZWpRblxxeV5qQWH2KU5mBREudVsm8LERJITyxJzU5NLUgtgskycXBKNTAuyn+95bMJh9WD 0/M5ak5JKaovvjBtXdy8dJ7ffC37A6Zd3BdYnJkm333K8LrJjn3n/Q5/Wxe5UuhAV8/WdNsb CmbFqTaCBp0ezNJTClYlXzNseP51/heGGecO1HwOYQz0W5q3b81SDY7Ftr2S6cs+Z5lO2Mjj 5Nj519NgZYYar0gAZxp3+iYlluKMREMt5qLiRAAO0RqGQQIAAA== Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Presented patch aims to move data necessary for correct CPU cooling device configuration from exynos_tmu_data.c to device tree. Signed-off-by: Lukasz Majewski --- Changes for v2: - None --- arch/arm/boot/dts/exynos4210-trats.dts | 15 ++++++++++++ arch/arm/boot/dts/exynos4210.dtsi | 20 ++++++++++++++++ arch/arm/boot/dts/exynos4212.dtsi | 20 ++++++++++++++++ arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 15 ++++++++++++ arch/arm/boot/dts/exynos4412-trats2.dts | 15 ++++++++++++ arch/arm/boot/dts/exynos4412.dtsi | 32 +++++++++++++++++++++++++ arch/arm/boot/dts/exynos5250.dtsi | 20 +++++++++++++++- 7 files changed, 136 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index b59019c..d9dd9a7 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -428,6 +428,21 @@ status = "okay"; }; + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 2 2>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 4 4>; + }; + }; + }; + }; + camera { pinctrl-names = "default"; pinctrl-0 = <>; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 807bb5b..10e8915 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -41,6 +41,26 @@ #clock-cells = <1>; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x900>; + cooling-min-level = <4>; + cooling-max-level = <2>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x901>; + }; + }; + sysram@02020000 { compatible = "mmio-sram"; reg = <0x02020000 0x20000>; diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 3c00e6e..6405954 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -22,6 +22,26 @@ / { compatible = "samsung,exynos4212", "samsung,exynos4"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA00>; + cooling-min-level = <13>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA01>; + }; + }; + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <18>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index eb1c08c..15d45f0 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -375,6 +375,21 @@ vtmu-supply = <&ldo10_reg>; status = "okay"; }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>; + }; + }; + }; + }; }; &pinctrl_1 { diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 121430d..396c525 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -786,4 +786,19 @@ pulldown-ohm = <100000>; /* 100K */ io-channels = <&adc 2>; /* Battery temperature */ }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>; + }; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index d8bc059e..9ed8925 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -22,6 +22,38 @@ / { compatible = "samsung,exynos4412", "samsung,exynos4"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA00>; + cooling-min-level = <13>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA01>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA02>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA03>; + }; + }; + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <20>; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index d55c1a2..a5bbc1a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -58,11 +58,14 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1700000000>; + cooling-min-level = <15>; + cooling-max-level = <9>; + #cooling-cells = <2>; /* min followed by max */ }; cpu@1 { device_type = "cpu"; @@ -241,6 +244,21 @@ clock-names = "tmu_apbif"; }; + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 9 9>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 15 15>; + }; + }; + }; + }; + serial@12C00000 { clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0";