From patchwork Fri Dec 19 13:23:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Padmavathi Venna X-Patchwork-Id: 5519261 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7432B9F4DC for ; Fri, 19 Dec 2014 13:31:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C180220145 for ; Fri, 19 Dec 2014 13:31:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EEA5620142 for ; Fri, 19 Dec 2014 13:31:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752241AbaLSNbf (ORCPT ); Fri, 19 Dec 2014 08:31:35 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:38478 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752177AbaLSNbe (ORCPT ); Fri, 19 Dec 2014 08:31:34 -0500 Received: from epcpsbgr4.samsung.com (u144.gpu120.samsung.co.kr [203.254.230.144]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NGU00AOE08KSD70@mailout1.samsung.com>; Fri, 19 Dec 2014 22:31:32 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.123]) by epcpsbgr4.samsung.com (EPCPMTA) with SMTP id 4C.B9.18167.2B824945; Fri, 19 Dec 2014 22:31:30 +0900 (KST) X-AuditID: cbfee690-f79ab6d0000046f7-f8-549428b2e99a Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 3F.61.20081.2B824945; Fri, 19 Dec 2014 22:31:30 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NGU009US0704GA0@mmp2.samsung.com>; Fri, 19 Dec 2014 22:31:30 +0900 (KST) From: Padmavathi Venna To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: kgene.kim@samsung.com, mturquette@linaro.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com Subject: [PATCH 1/4] clk: samsung: exynos7: add gate clock for DMA block Date: Fri, 19 Dec 2014 18:53:44 +0530 Message-id: <1418995427-7712-2-git-send-email-padma.v@samsung.com> X-Mailer: git-send-email 2.2.0 In-reply-to: <1418995427-7712-1-git-send-email-padma.v@samsung.com> References: <1418995427-7712-1-git-send-email-padma.v@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrJLMWRmVeSWpSXmKPExsWyRsSkWneTxpQQg71rTSzmHznHatG74Cqb xabH11gtZpzfx2TxdMJFNovDb9pZLVbt+sPowO6xc9Zddo871/aweWxeUu/Rt2UVo8fnTXIB rFFcNimpOZllqUX6dglcGb2vdjMX/OOumP/1HGMD41yuLkZODgkBE4mbZ+6wQNhiEhfurWfr YuTiEBJYyihxc/9sIIcDrOhnSwhEfDqjxLIJa1khnAlMEhcvb2UEKWIT0JFoOesCMkhEIFNi 091tjCA2s0CixJf9c5hBbGEBD4lr08+CLWMRUJVoP7aKFcTmFXCS+H/9DCvEEXISW249Ygex OQWcJc63nweLCwHV3G+czA6yV0JgHrvEv9PLWSEGCUh8m3yIBeJQWYlNB5gh5khKHFxxg2UC o/ACRoZVjKKpBckFxUnpRSZ6xYm5xaV56XrJ+bmbGIEhfvrfswk7GO8dsD7EKMDBqMTD+6B4 cogQa2JZcWXuIUZToA0TmaVEk/OBkZRXEm9obGZkYWpiamxkbmmmJM77WupnsJBAemJJanZq akFqUXxRaU5q8SFGJg5OqQZGT5WZym/FjyxPDVt09/QiF3+7xL5tS6SVRCcwLZS/Xc6dmJ94 6rOkx1e/mAW9W2L7Wv1vvz4T1JfyyZz//bmrzQfr15SEtzKJViyRDtBdFbVp5Qum1t1nN2df PXN+dXbamif338p5vXlVwekTetZdU7TaofhP4Y2eG3caHq83ZtvA51KnNOmZEktxRqKhFnNR cSIAONvAyWwCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrMIsWRmVeSWpSXmKPExsVy+t9jQd1NGlNCDB7+1raYf+Qcq0Xvgqts FpseX2O1mHF+H5PF0wkX2SwOv2lntVi16w+jA7vHzll32T3uXNvD5rF5Sb1H35ZVjB6fN8kF sEY1MNpkpCampBYppOYl56dk5qXbKnkHxzvHm5oZGOoaWlqYKynkJeam2iq5+AToumXmAJ2h pFCWmFMKFApILC5W0rfDNCE0xE3XAqYxQtc3JAiux8gADSSsYczofbWbueAfd8X8r+cYGxjn cnUxcnBICJhI/GwJ6WLkBDLFJC7cW8/WxcjFISQwnVFi2YS1rBDOBCaJi5e3MoI0sAnoSLSc dQFpEBHIlNh0dxsjiM0skCjxZf8cZhBbWMBD4tr0sywgNouAqkT7sVWsIDavgJPE/+tnWCGW yUlsufWIHcTmFHCWON9+HiwuBFRzv3Ey+wRG3gWMDKsYRVMLkguKk9JzDfWKE3OLS/PS9ZLz czcxgiPomdQOxpUNFocYBTgYlXh4OwonhwixJpYVV+YeYpTgYFYS4f0oPCVEiDclsbIqtSg/ vqg0J7X4EKMp0FUTmaVEk/OB0Z1XEm9obGJuamxqaWJhYmapJM6rZN8WIiSQnliSmp2aWpBa BNPHxMEp1cCovennL11nztkWbK6OLF+Zk0Wn/D1dpz2vgWfjItkcrXXX6mezn/7q3H7oy/xf kru+H3r/T33u9LeXL7s4xjK+ub10Il+ra7vRhh3nKjMVf/UXRhxy8NqwW9bzimF/z7UwgS1G 7y8qFt8/YKe+zuvd2n+LxXZuyGGyXHdI8dcl/zb3jQHJD5pVlFiKMxINtZiLihMB5KI+kbYC AAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add support for PDMA0 and PDMA1 gate clks. Signed-off-by: Padmavathi Venna --- drivers/clk/samsung/clk-exynos7.c | 4 ++++ include/dt-bindings/clock/exynos7-clk.h | 4 +++- 2 files changed, 7 insertions(+), 1 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c index 3a56875..954f9a0 100644 --- a/drivers/clk/samsung/clk-exynos7.c +++ b/drivers/clk/samsung/clk-exynos7.c @@ -711,6 +711,10 @@ static struct samsung_gate_clock fsys0_gate_clks[] __initdata = { GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS00, 19, 0, 0), + GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user", + ENABLE_ACLK_FSYS00, 3, 0, 0), + GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user", + ENABLE_ACLK_FSYS00, 4, 0, 0), GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user", ENABLE_ACLK_FSYS01, 29, 0, 0), diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h index eef2116..a6c4d8e 100644 --- a/include/dt-bindings/clock/exynos7-clk.h +++ b/include/dt-bindings/clock/exynos7-clk.h @@ -89,7 +89,9 @@ #define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6 #define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7 #define OSCCLK_PHY_CLKOUT_USB30_PHY 8 -#define FSYS0_NR_CLK 9 +#define ACLK_PDMA0 9 +#define ACLK_PDMA1 10 +#define FSYS0_NR_CLK 11 /* FSYS1 */ #define ACLK_MMC1 1